Zero-temperature-coefficient biasing point of 2.4-GHz LNA in PD SOI CMOS technology

Kaamouchi, M. El; Moussa, M. Si; Raskin, J.-P.; Vanhoenacker‐Janvier, Danielle

doi:10.1109/eumc.2007.4405390

Cited by 10 publications

(12 citation statements)

References 6 publications

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“…Now using the assumption α μ ≈ -2 [19] along with Eq. 10and 5, a simple expression for the ZTC gate-bulk voltage (V GZ -related to i fz ) is found (11) Eq. (11) presents the same result already derived from the strong inversion quadratic model in Eq.…”

Section: A Mosfet Bias Ztc Conditionmentioning

confidence: 99%

“…Usually, the temperature sensitivity is not considered in these designs and often is not even measured (in some works the tem-perature sensitivity is implicitly analyzed in the corner PVT simulation). Among those few CMOS RF thermal-care designs, it is the work published in [11], at which the high temperature effects on the LNA gain and on the Partially Depleted Silicon-on-Insulator (PD-SOI) transistors were observed and investigated in order to analyze the LNA behavior versus temperature. This work uses the GZTC condition as bias point but there is no any kind of modeling explaining how the sizing has been made.…”

Section: Introductionmentioning

confidence: 99%

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Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Toledo¹,

Klimach²,

Cordova³

et al. 2020

JICS

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Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

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Section: A Mosfet Bias Ztc Conditionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Toledo¹,

Klimach²,

Cordova³

et al. 2020

JICS

View full text Add to dashboard Cite

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“…Regarding high temperature LNAs, [8] details a fully integrated 130-nm SOI CMOS 2.4 GHz LNA with temperature compensation from 25°C to 200°C. The LNA uses a cascode inductive degeneration topology and zero temperature coefficient transconductance (ZTC gm ) bias point.…”

Section: B Existing High Temperature and Gan Lnasmentioning

confidence: 99%

A high temperature wideband low noise amplifier for downhole applications

Cunningham

Koh

2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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As the oil industry continues to drill deeper to reach new wells, electronics are required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTC MAG ) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25 μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230°C with a minimum noise figure (NF) of 2.0 dB, average gain of 16.1 dB, and input P1dB of 4.0 dBm from 230.5 -285.5 MHz. The maximum variation with temperature from 25°C to 230°C is 1.53 dB for NF and 0.65 dB for gain.

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“…For gate voltages lower than ZTC, the decrease of threshold voltage is dominant, as a matter of fact drain current increases with temperature, while for gate voltages higher than ZTC, the mobility degradation predominates and drain current decreases with temperature. The ZTC is a very important bias point for analog designers as it corresponds to a gate voltage at which the device DC performance remains constant with temperature [19], [23], [24].…”

Section: Ztc Bias Pointmentioning

confidence: 99%

ZTC bias point of advanced fin based device: The importance and exploration

2015

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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0 C to 225 0 C is reviewed to extend the benchmark of device scalability. The impact of fin height (H Fin), fin width (W Fin), and temperature (T) on immense performance metrics including on-off ratio (I on /I off), transconductance (g m), gain (A V), cutoff frequency (f T), static power dissipation (P D), energy (E), energy delay product (EDP), and sweet spot (g m f T /I D) of the FinFET is successfully carried out by commercially available TCAD simulator Sentaurus TM from Synopsis Inc.

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Zero-temperature-coefficient biasing point of 2.4-GHz LNA in PD SOI CMOS technology

Cited by 10 publications

References 6 publications

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

A high temperature wideband low noise amplifier for downhole applications

ZTC bias point of advanced fin based device: The importance and exploration

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