Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

Hanna, Amir; Ghoneim, Mohamed T.; Bahabry, Rabab R.; Hussain, Aftab M.; Hussain, Muhammad Mustafa

doi:10.1063/1.4836235

Cited by 13 publications

(12 citation statements)

References 12 publications

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“…Although, it is less expensive compared to the first approach, the TFT properties suffer immensely from both gate leakage and gate-to source/drain overlap capacitance. The new approach -we are reporting improves Om per unit device width by increasing the device width vertically without chip area penalty, as well as, improves the field effect mobility, liFE, due to high electric field at fin corners, which enhances the field effect mobility, as reported in our previous work [5][6][7].…”

Section: Introductionmentioning

confidence: 67%

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

Hanna

Hussain

2015

2015 73rd Annual Device Research Conference (DRC)

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We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling.

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Section: Introductionmentioning

confidence: 67%

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

Hanna

Hussain

2015

2015 73rd Annual Device Research Conference (DRC)

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“…A thin dual gate approach on SOI with the volume inversion is reported in [5], [19]. The another representation using 2D planar UTB and 3D non-planar approach is first given by [20], [21] later provides the detailed analysis with several performance metrics analyzed and reported in [22]- [24]. The significance of the FinFET provides better layout area efficiency in the digital circuits [25].…”

Section: Device Description and Simulation Frameworkmentioning

confidence: 99%

Impact of channel engineering (Si1-0.25Ge0.25) technique on GM(transconductance) and its higher order derivatives of 3D conventional and wavy Junctionless FinFETs (JLT)

et al. 2018

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The paper explores the analog analysis and higher order derivatives of drain current (I D ) at gate source voltage (V GS ), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium (Si 1-0.25 Ge 0.25 ) device layer. In view of this, the performances are carried out for different gate length (L G ) values (15-30 nm) and current characteristics determined by maintaining constant ON current (I ON 10 -5 ) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high I D induces as the L G scales down. With respect to this the constant I ON determine I D , transconductance (g m ), transconductance generation factor (TGF) and its higher order terms (g \ m , and g \\ m ) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (N D = 1.7x10 19 cm -3 ) and metal workfunction (ϕ M = 4.6 eV) are responsible to achieving reduced SCEs.

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“…1 These challenges can be mitigated by novel channel materials with better charge transport properties. 2 Prominent among the alternative channel materials being studied are graphene and other single atomic layer materials, 3-5 III-V semiconductors, 6-8 oxide semiconductors, 9 and carbon nanotubes. 10 Even in case of novel channel materials, a silicon wafer is still used as the starting substrate because of ease of processing and low cost.…”

Section: Introductionmentioning

confidence: 99%

Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

Hussain

Singh

Fahad

et al. 2014

Journal of Applied Physics

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We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well as experimentally by fabricating MOSFETs. Our study suggests that the alloy offers interesting possibilities in the realm of silicon band gap tuning. We have explored diffusion of tin (Sn) into the industry's most widely used substrate, silicon (100), as it is the most cost effective, scalable and CMOS compatible way of obtaining SiSn. Our theoretical model predicts a higher mobility for p-channel SiSn MOSFETs, due to a lower effective mass of the holes, which has been experimentally validated using the fabricated MOSFETs. We report an increase of 13.6% in the average field effect hole mobility for SiSn devices compared to silicon control devices. V C 2014 AIP Publishing LLC. [http://dx.

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Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

Abstract: High performance thin film transistor with low temperature atomic layer deposition nitrogen-doped ZnO

Cited by 13 publications

References 12 publications

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

Impact of channel engineering (Si1-0.25Ge0.25) technique on GM(transconductance) and its higher order derivatives of 3D conventional and wavy Junctionless FinFETs (JLT)

Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

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