Impact of channel engineering (Si1-0.25Ge0.25) technique on GM(transconductance) and its higher order derivatives of 3D conventional and wavy Junctionless FinFETs (JLT)

Abstract

The paper explores the analog analysis and higher order derivatives of drain current (I D ) at gate source voltage (V GS ), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium (Si 1-0.25 Ge 0.25 ) device layer. In view of this, the performances are carried out for different gate length (L G ) values (15-30 nm) and current characteristics determined by maintaining constant ON current (I ON 10 -5 ) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high I D induces as the L G scales down. With respect to this the constant I ON determine I D , transconductance (g m ), transconductance generation factor (TGF) and its higher order terms (g \ m , and g \\ m ) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (N D = 1.7x10 19 cm -3 ) and metal workfunction (ϕ M = 4.6 eV) are responsible to achieving reduced SCEs.

Inverted ‘T’ Junctionless FinFET (ITJL FinFET): Performance Estimation through Device Geometry Variation

“…Increasing the spacer length offers longer effective channel length and influence the lateral extension of depletion width. This causes an additional outer fringing capacitance 37,38 and results in device performance improvement.…”