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Local electrical property of coincidence site lattice boundaries (CSLBs) in location-controlled silicon islands, which are fabricated using micro-Czochralski process (grain filter), was characterized by scanning spreading resistance microscopy (SSRM) and scanning spreading resistance microscopy (SCM). Some CSLBs found in a silicon island are analyzed as Sigma 3 and Sigma 9 by electron back scattering diffraction pattern. These CSLBs are determined as {111}Sigma 3 and {221}Sigma 9 by referring to previous observation results made by transmission electron microscopy. {111}Sigma3 CSLBs shows no activity for SCM or SSRM; this is consistent with previous prediction that {111}Sigma 3 CSLB is not electrical active. We verified a capability of SCM and SSRM for characterizing local electrical property of coincidence site lattice boundary in silicon.

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. Using a finite element method (FEM) simulation, the damage to the bottom layer devices during laser crystallization of the top layer silicon layer has been investigated. N-channel metal-oxide-semiconductor (n-MOS) mobilities are 565 and 393 cm 2 V À1 s À1 and p-channel MOS (p-MOS) mobilities are 159 and 141 cm 2 V À1 s À1 , for the top and bottom layers respectively. A threedimensional (3D) complementary MOS (CMOS) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. #