a [ b [ c [ d [ e [ j [ k [ o [ t [ The CDF experiment's Silicon Vertex Trigger is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 µsec pipeline. SVT's 35 µm impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common inter-board data link, and a universal "Merger" board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.

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Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times.

The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology.Index Terms-Parallel processing, particle tracking, pattern matching, triggering, very large scale integration (VLSI).

Abstract-We propose precise and fast-track reconstruction at hadron collider experiments, for use in online trigger decisions. We describe the features of fast-track (FTK), a highly parallel processor dedicated to the efficient execution of a fast-tracking algorithm. The hardware-dedicated structure optimizes speed and size; these parameters are evaluated for the ATLAS experiment. We discuss some applications of high-quality tracks available to the trigger logic at an early stage, by using the LHC environment as a benchmark. The most interesting application is online selection of b-quarks down to very low transverse momentum, providing interesting hadronic samples: examples are Z 0 b b, potentially useful for jet calibration, and multi-b final states for supersymmetric Higgs searches. The paper is generated from outside the ATLAS experiment and has not been discussed by the ATLAS collaboration.Index Terms-Parallel processing, particle tracking, pattern matching, triggering, very large scale integration. A. Cerri and L. Vacavant are with the Lawrence Berkeley National Laboratory, Berkeley, CA 94720 USA (e-mail: acerri@lbl.gov; lvacavant@lbl.gov).S. Giagu and L. Zanello are with the Dipartimento di Fisica, La Sapienza, 00185 Rome, Italy (e-mail: stefano.giagu@roma1.infn.it; lucia.zanello@roma1.infn.it).G. Iannaccone is with Dipartimento di Ingegneria dell'Informazione, Università di Pisa, I-56126 Pisa, Italy (e-mail: g.iannaccone@iet.unipi.it).G. Punzi and I. Vivarelli are with Scuola Normale, 56126 Pisa, Italy (e-mail: giovanni.punzi@pi.infn.it; iacopo.vivarelli@pi.infn.it).M. Rescigno is with Istituto Nazionale di Fisica Nucleare, 00185 Rome, Italy (e-mail: marco.rescigno@roma1.infn.it).M. Shochet is with the Enrico Fermi Institute and the Department of Physics, University of Chicago, Chicago, IL 60637 USA (e-mail: shochet@hep.uchicago.edu).S. Torre is with the Istituto Nazionale di Fisica Nucleare, Pisa, Italy, and also with the Dipartimento di Fisica, Università di Siena, 53100 Siena, Italy (e-mail: stefano.torre@pi.infn.it).Digital Object Identifier 10.1109/TNS.2004.828639 Fig. 1. The FTK processor has access to the tracker data of events selected by the LVL1. The FTK performs substantial data reduction by selecting high P track candidates and organizing them with their hits into standard DAQ buffer memories, ready for the high-level triggers (level-2 and level-3).