This work looks at the application of chromeless phase-shift masks to sub-100 nm gate length SOT transistor fabrication. The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask which also patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes.The chromeless mask fabrication approach is discussed. A simple, single step dry etch is used with no minimum geometry features, thus simplifying mask fabrication. We employed an 0.6 NA, DUV (248 nm) tool for this work together with commercially available resists and anti-reflection layers. Lithography results for k1 factors down to 0.10 (isolated) and 0.3 (dense) are presented. This corresponds to CD's of4O nm (isolated) and 125 nm (dense) on our Canon EX-4, 248nm stepper. Excellent pattern transfer into polysilicon was achieved using a high density plasma etch process producing gate features down to 25 nm linewidths.We discuss the application of this method to the fabrication of sub-100 nm gatelength fully-depleted SOT CMOS transistors. We have fabricated SOT CMOS transistors with excellent short channel behavior down to 50 nm physical gate lengths. This method enables the development of deep sub-100 nm gate length CMOS technologies using standard 248-nm exposure sources. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 08/10/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx I) IntroductionThe continued progress of the semiconductor industry along the fURS Roadmap has begun to require lithography capability with sub-wavelength 1 Current 0. 1 8 pm design rule devices are being produced using 248 nm lithography tools, with further shrinks to 0. 1 5 im and possibly 0.13 im being contemplated.2 These lithography requirements have increased the interest in resolution enhancement techniques in order to obtain good resolution and process latitude at ever decreasing ki factors. Strong phase-shift methods3 such as alternating aperture and chromeless offer the largest potential resolution increase, if they can be incorporated into a practical process module. The ultimate practical limit of these methods has yet to be determined.This work looks at the application of chromeless phase-shift masks to sub-100 nm gate length fully depleted silicon on insulator (FDSOI) CMC)S transistor fabrication. The double exposure technique of Numerical Technologies is extended to the chromeless case. Fig. 1 is a schematic diagram of this approach.4 Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates, and the second is a binary trim mask which patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating ape...

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