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A: CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel sizes larger than approximately forty micrometers. This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations. The studied design uses a 0.18 µm process implemented on a high-resistivity epitaxial layer. K: Solid state detectors, Detector modelling and simulations, Charge induction, Radiationhard detectors A X P : 1903.10190

This paper describes a solid-state sensor for ultra-high-speed (UHS) imaging. The 'Kirana' sensor was designed and manufactured in a 180 nm CMOS technology to achieve full-frame 0.7 Megapixel video capture at speeds at 2 MHz. The 30 µm pixels contain a pinned photodiode, a set of 180 low-leakage storage cells, a floating-diffusion, and a source follower output structure. Both the individual cells and the way they are arranged in the pixel are novel. The pixel architecture allows correlated double sampling for low noise operation.In the fast mode, the storage cells are operated as a circular buffer, where 180 consecutive frames are stored until receipt of a trigger; up to 5 video-bursts per second can be read out. In the 'slow' mode, the storage cells act like a pipeline; the sensor can be read out like a conventional sensor at a continuous frame rate of 1,180 fps. The sensor architecture is fully scalable in resolution since memory cells are located inside each pixel. The pixel architecture is scalable in memory depth (number of frames) as a trade-off with pixel size, dependent on application. The present implementation of 0.7 Mpixels has an array focal plane which is optimized for standard 35 mm optics, whilst offering a competitive 180-frame recording depth.The sensor described has been manufactured and is currently being characterized. Operation of the sensor in the fast mode at 2 million frames per second has been achieved. Details on the camera/sensor operation are presented together with first experimental results.

Organic photodiodes (OPDs) for its interesting optoelectronic properties has the potential to be utilized with complementary metal-oxide-semiconductor (CMOS) circuit for imaging, automotive, and security based applications. To achieve such a hybrid device as an image sensor, it is imperative that the quality of the OPD remains high on the CMOS substrate and that it has a well-connected optoelectronic interface with the underneath readout integrated circuit (ROIC) for efficient photogeneration and signal readout. Here, we demonstrate seamless integration of a thermally deposited visible light sensitive small molecule OPD on a standard commercial CMOS substrate using optimized doped PCBM buffer layer. Under a standard power supply voltage of 3 V, this hybrid device shows an excellent photolinearity in the entire bias regime, a high pixel sensitivity of 2 V/Lux.sec, a dynamic range (DR) of 71 dB, and a low dark leakage current density of 1 nA/cm2. Moreover, the integrated OPD has a minimum bandwidth of 400 kHz. The photoresponse nonuniformity being only 1.7%, achieved under research lab conditions, strengthens the notion that this fully-CMOS compatible technology has the potential to be applied in high-performance large-scale imaging array.

Effects of interfaces and thermal annealing on the electrical performance of the SiO 2 /Si 3 N 4 /Al 2 O 3 ͑ONA͒ stacks in nonvolatile memory devices were investigated. The results demonstrated the principal role of Si 3 N 4 /Al 2 O 3 and Al 2 O 3 /metal-gate interfaces in controlling charge retention properties of memory cells. Memory devices that employ both electron and hole trappings were fabricated using a controlled oxidation of nitride surface prior to the Al 2 O 3 growth, a high-temperature annealing of the ONA stack in the N 2 +O 2 atmosphere, and a metal gate electrode having a high work function ͑Pt͒. These devices exhibited electrical performance superior to that of their existing SiO 2 /Si 3 N 4 / SiO 2 analogs.