This paper presents a fully-integrated performanceon-demand receiver front-end for GSM/EDGE/W-CDMA/ CDMA2000 multi-mode cellular applications. The design's noise figure, linearity and selectivity are adapted depending on current environmental conditions and the selected standard to guarantee lowest overall power consumption. The single-chip zero-IF receiver comprises two self-matched LNAs for high/low-band, the demodulator and a fully-integrated ΔΣ−fractional−N PLL. The integration of I/Q-ADCs and a digital front-end (DFE) enables an efficient 3rd-order analog baseband filter. Accurate channel and matched filtering, sample-rate conversion and dynamic-range control are achieved in the DFE allowing for greater flexibility. In the absence of any blocker the performance of demodulator, VCO, analog baseband filter and DFE are adapted to reduce the current consumption up to 42 % versus the full-featured mode. The receiver has been fabricated in a 0.13 μm CMOS process and occupies 8 mm 2 die area. The design is verified by error-vector-magnitude (EVM) measurements exhibiting 3.9 % for W-CDMA and 3.1 % for CDMA2000.

No abstract

The ongoing evolution from 2G to 3G and beyond confronts the cellular market with the challenges of a broad diversity of communication standards. Furthermore, increasing levels of integration with minimum external component count, advances in semiconductor process technology, and the requirement for multi-mode operation are pivotal demands of the RF-IC manufactures to achieve fast design cycles and low product cost. As a result, reconfiguration of the wireless terminal has become the key issue in the design of wireless terminals. This paper discusses the requirements for multi-mode reconfigurable wireless receivers with focus put onto mixed-signal and digital enhancements to traditional analog front-end designs. The flexibility a digitalfront-end (DFE) introduces is studied with respect to the main cellular communication standards (GSM/EDGE, CDMA2000, W-CDMA/HSDPA, and LTE) and satellite navigation systems (GPS, Galileo), with considerations of impacts on the capability of an implementation of a software-defined-radio (SDR).

No abstract

Abstract. The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF), and 1dB compression point (P1dB) of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.