This paper presents a fully-integrated performanceon-demand receiver front-end for GSM/EDGE/W-CDMA/ CDMA2000 multi-mode cellular applications. The design's noise figure, linearity and selectivity are adapted depending on current environmental conditions and the selected standard to guarantee lowest overall power consumption. The single-chip zero-IF receiver comprises two self-matched LNAs for high/low-band, the demodulator and a fully-integrated ΔΣ−fractional−N PLL. The integration of I/Q-ADCs and a digital front-end (DFE) enables an efficient 3rd-order analog baseband filter. Accurate channel and matched filtering, sample-rate conversion and dynamic-range control are achieved in the DFE allowing for greater flexibility. In the absence of any blocker the performance of demodulator, VCO, analog baseband filter and DFE are adapted to reduce the current consumption up to 42 % versus the full-featured mode. The receiver has been fabricated in a 0.13 μm CMOS process and occupies 8 mm 2 die area. The design is verified by error-vector-magnitude (EVM) measurements exhibiting 3.9 % for W-CDMA and 3.1 % for CDMA2000.

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