Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are poorly matched to conventional microprocessor architectures, they are a good fit for modern VLSI technology with its high arithmetic capacity but limited global bandwidth. The stream programming model, in which an application is coded as streams of data records passing through computation kernels, exposes both parallelism and locality in media applications that can be exploited by VLSI architectures. The Imagine architecture supports the stream programming model by providing a bandwidth hierarchy tailored to the demands of media applications. Compared to a conventional scalar processor, Imagine reduces the global register and memory bandwidth required by typical applications by factors of 13 and 21 respectively. This bandwidth efficiency enables a single chip Imagine processor to achieve a peak performance of 16.2GFLOPS (single-precision floating point) and sustained performance of up to 8.5GFLOPS on media processing kernels.

Smart pixel architectures offer important new opportunities for low cost, portable image processing systems. They provide greater I/O bandwidth and computing performance than systems based on CCD and microprocessors. However, finding a balance between performance, flexibility, efficiency, and cost depends on an evaluation of target applications. This paper describes several promising architectural approaches for the realization of videoputer systems and outlines example implementations being pursued at Georgia Tech.

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We present for the first time a three-dimensional (3-D) Si CMOS interconnection system consisting of three layers of optically interconnected hybrid integrated Si CMOS transceivers. The transceivers were fabricated using 0.8-m digital Si CMOS foundry circuits and were integrated with long wavelength InP-based emitters and detectors for through-Si vertical optical interconnections. The optical transmitter operated with a digital input and optical output with operation speeds up to 155 Mb/s. The optical receiver operated with an external optical input and a digital output up to 155 Mb/s. The transceivers were stacked to form 3-D through-Si vertical optical interconnections and a fabricated three-layer stack demonstrated optical interconnections between the three layers with operational speed of 1 Mb/s and bit-error rate of 10 09. Index Terms-Optical interconnect, 3-D integration. I. INTRODUCTION O NE LIMITATION in the development of sophisticated smart pixel systems lies with the interconnection of the pixels to advanced processing circuitry. Often, the limited Si area under or surrounding each pixel is insufficient for high levels of VLSI signal processing. One possible solution is to increase the die size and maintain the pixel dimensions to allow more processing on the same circuit plane as the pixel array, but this approach is unacceptable because it decreases the fill factor of the associated image array. A better solution would be to develop three-dimensional (3-D) interconnections from the image array to subsequent advanced processing layers. This is essentially an interconnection problem, which also plagues electronic systems.

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