No abstract

No abstract

No abstract

No abstract

We present for the first time a three-dimensional (3-D) Si CMOS interconnection system consisting of three layers of optically interconnected hybrid integrated Si CMOS transceivers. The transceivers were fabricated using 0.8-m digital Si CMOS foundry circuits and were integrated with long wavelength InP-based emitters and detectors for through-Si vertical optical interconnections. The optical transmitter operated with a digital input and optical output with operation speeds up to 155 Mb/s. The optical receiver operated with an external optical input and a digital output up to 155 Mb/s. The transceivers were stacked to form 3-D through-Si vertical optical interconnections and a fabricated three-layer stack demonstrated optical interconnections between the three layers with operational speed of 1 Mb/s and bit-error rate of 10 09. Index Terms-Optical interconnect, 3-D integration. I. INTRODUCTION O NE LIMITATION in the development of sophisticated smart pixel systems lies with the interconnection of the pixels to advanced processing circuitry. Often, the limited Si area under or surrounding each pixel is insufficient for high levels of VLSI signal processing. One possible solution is to increase the die size and maintain the pixel dimensions to allow more processing on the same circuit plane as the pixel array, but this approach is unacceptable because it decreases the fill factor of the associated image array. A better solution would be to develop three-dimensional (3-D) interconnections from the image array to subsequent advanced processing layers. This is essentially an interconnection problem, which also plagues electronic systems.