A three-layer 3D silicon system using through-Si vertical optical interconnections and Si CMOS hybrid building blocks

Abstract

We present for the first time a three-dimensional (3-D) Si CMOS interconnection system consisting of three layers of optically interconnected hybrid integrated Si CMOS transceivers. The transceivers were fabricated using 0.8-m digital Si CMOS foundry circuits and were integrated with long wavelength InP-based emitters and detectors for through-Si vertical optical interconnections. The optical transmitter operated with a digital input and optical output with operation speeds up to 155 Mb/s. The optical receiver operated with an external optical input and a digital output up to 155 Mb/s. The transceivers were stacked to form 3-D through-Si vertical optical interconnections and a fabricated three-layer stack demonstrated optical interconnections between the three layers with operational speed of 1 Mb/s and bit-error rate of 10 09. Index Terms-Optical interconnect, 3-D integration. I. INTRODUCTION O NE LIMITATION in the development of sophisticated smart pixel systems lies with the interconnection of the pixels to advanced processing circuitry. Often, the limited Si area under or surrounding each pixel is insufficient for high levels of VLSI signal processing. One possible solution is to increase the die size and maintain the pixel dimensions to allow more processing on the same circuit plane as the pixel array, but this approach is unacceptable because it decreases the fill factor of the associated image array. A better solution would be to develop three-dimensional (3-D) interconnections from the image array to subsequent advanced processing layers. This is essentially an interconnection problem, which also plagues electronic systems.

Transfer of InP epilayers by wafer bonding

“…Indirect bonding technologies that are easier to use include adhesive bonding or eutectic bonding, where intermediate layers of polymers [20][21][22][23][24][25][26][27][28]36], spin-on-glasses [37] and metals [17][18][19]38]. These methods may ease bonding of dies to wafers, reducing the amount of III-V material to be used on a Si wafer.…”

Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects

“…If the substrate material is transparent to the wavelength of light being used, no specific waveguiding structure is required for through-substrate optical transmission. While through-wafer optical interconnections using this phenomenon have been proposed [63][64][65], this approach limits the selection of substrate materials and useful optical wavelengths of operation. In this work, a waveguiding approach is adopted for optical signal transmission.…”

Fabrication of Ti-Si-Ti Metal-Semiconductor-Metal Photodetectors Using Low Temperature Rapid Thermal Annealing

“…Planar Schottky Metal-Semiconductor-Metal (MSM) photodetector has been subject of study in the last years due to ease of fabrication, low capacitance per unit area (in comparison with conventional vertical p i n photodiodes) and fabrication compatibility with conventional MOS processes, making it suitable to be applied in optoelectronic integrated circuits (OEIC) [1], optical interconnections on chip-to-chip level [2][3] and integrated optical sensors [4][5].…”