This article is aimed at extracting an accurate multibias small signal equivalent circuit for on‐wafer microwave HEMTs, which are based on AlGaAs/GaAs heterostructure. The main advantage of the on‐wafer characterization consists of having the possibility to determine the real microwave performance of the transistors, since the inclusion of additional parasitic effects, such as in the case of the packaging and wire bonding, are avoided. The presented small signal modeling technique is direct. As a matter of fact, the equivalent circuit elements are extracted from scattering parameter measurements by using only analytical formulas, without any optimization procedures. The validity of the obtained circuit models is successfully verified by comparing simulated and measured data of scaled GaAs HEMTs up to 50 GHz. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1958–1963, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24492

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process

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In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18µm CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.

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