A Methodology for the Design of MOS Current-Mode Logic Circuits

Abstract

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process

A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates

“…Indeed, both noise margin and propagation delay depend on it [1,2]. The expression of the gain is where:…”

“…For that reason, g ds is generally neglected [1,2]. Unfortunately, as shown by simulation results, that can cause large errors in the value of A v .…”

“…The current interest in MCML circuits is mainly due to their use in mixedsignal integrated circuits [1,2]. Major advantages of them are low crosstalk due to the low output voltage swing, good noise immunity to supply noise due to their differential nature and low generated supply noise due to supply current almost constant during the output-voltage switching.…”

“…Since their delay is an increasing function of that current [1,2], the faster are the circuits the more energy they consume. Hence, it is crucial to be able to quantify the tradeoff that can be realized between speed and energy in order to design energyefficient MCML circuits.…”

“…That also occurs in designs optimized for speed, when using sub-100 nm technologies. Unfortunately, at the best of the author's knowledge, all the delay models for MCML circuits utilized in the technical literature are based on the assumption that the NMOS transistors of the pull-down network are operating in the strong inversion region [1,2]. So, in order to quantify the energy-delay tradeoff, it is necessary to develop a delay model valid in all the operation regions of the MOS transistor, namely, weak inversion (subthreshold) moderate inversion (near-threshold) and strong inversion.…”