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In this work we study the self-heating effect (SHE) in nanoscale Silicon on Insulator Junctionless (SOI JL) FinFET transistor with fin cross section in rectangular, trapeze and triangle form. The lattice temperature dependence on the channel length as well as on buried oxide thickness is considered. It is shown that for considered transistor structure the lattice temperature in the middle of the channel is lower than at lateral sides, near source and drain. Also, we have found at the same conditions the lattice temperature depends on shape of channel cross section too.

Short channel effects, such as DIBL are compared for SOI-FinFETs with different silicon body geometries. The original device considered was straight without narrowing at the top and a set of devices that exhibit the mentioned narrowing, up to the extreme case where the top of the gate has no surface and so the body cross-section is essentially a triangle. We have studied five different variations from the original geometry of a 25 nm gate length SOI-FinFET device with 1.5 nm thick oxide layer. The P-type channel had a doping concentration of 10 15 cm −3 and n-type S/D areas are doped at concentrations of 10 20 cm −3 . The silicon body of the device accordingly had a height of 30 nm and a width of 12 nm. Simulation results show the source-drain barrier decreasing with increasing the upper body thickness. The DIBL effect of the considered FinFETs depends on upper body thickness, tending to increase with thicker upper body widths. Results of a comparison of two devices with different shapes but with the same cross-sectional area shows the relationship mainly depends on the shape rather than the cross-section area of the device body.