No abstract

No abstract

No abstract

We report on a 28nm product prototype test vehicle assembled back-to-face with a 4Gb 3× nm Wide I/O DRAM chip using Through Si Stacking (TSS) technology. The high bandwidth interface of the digital chip to the wide I/O memory chip is enabled by ∼1200 μ-bump joints with pitch as small as 40μm allowing for wide memory bandwidth. With appropriate chip floor-planning, we demonstrate the mitigation of any impact to digital circuit performance and yield from TSS and the possibility to re-use 2D circuit IP in a 3D product with minimal die size growth. Our 3DIC assembly process allows for a compact form-factor package with <1mm thickness. As part of an integrated product solution, we include a test methodology with test stages distributed throughout the integration flow which allow for selection of known-good die to maximize assembly yield.

No abstract