No abstract

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.Index Terms-Microbumps, 3-D integration, through silicon via.

No abstract

A metastable phase of Sn has been found to co-exist with β-Sn in Pb-free SnAg microbumps in 3D integrated circuit technology. Synchrotron microbeam x-ray diffraction, high-resolution TEM imaging and selected-area electron diffraction were used to confirm the metastable phase, which has a orthorhombic lattice, with lattice parameter a = 0.635 nm, b = 0.639 nm, and c = 1.147 nm. Its composition is Sn containing a few percent of Ni. A higher rate of nucleation might have enabled its formation.

In system level electromigration test of 2.5D integrated circuits, a failure mode due to synergistic effect of Joule heating and electromigration has been found. In the test circuit, there are three levels of solder joints, two Si chips (one of them has through-Si-via), and one polymer substrate. In addition, there are two redistribution layers; one between every two levels of solder joints. We found that the redistribution layer between the flip chip solder joints and micro-bumps is the weak-link and failed easily by burn-out in electromigration test. The failure is time-dependent with sudden resistance increase. Preliminary simulation results show that Joule heating has a positive feedback to electromigration in the redistribution layer and caused the thermal run-away failure. Joule heating becomes an important reliability issue in the future scaling of semiconductor devices.