Whereas the introduction of 3D-dimensional devices such as FINFET's may be a solution for next generation technologies, they do represent significant challenges with respect to the doping strategies and the junction characterization.Aiming at a conformal doping of the source/drain regions in a FINFET in order to induce a conformal under diffusion and homogenous device operation, one can quickly recognize that classical beam implants fail to fulfill these needs, in particular when considering closely spaced fin's. Indeed the effects of different implant angles (top vs bottom) and the concurrent variation in projected range, dose retention and sputtering as well as the effect of the wafer rotation when tilting is used, all lead to a non-conformal doping. Alternative processes such as vapor phase deposition (VPD) or plasma doping are presently being considered, as they hold the promise of conformality. Using VPD or Atomic Layer Doping dopant atoms are deposited on the surface through thermal decomposition of typical chemical vapor deposition precursors and are subsequently in diffused. Good conformality (~ 93 % for sidewall vs. top dose), defect free junctions and high activation levels are the positive points of this process. Plasma immersion doping is an alternative approach which is easier to integrate (similar to ion implantation) and suitable for p-and n-type doping. Whereas it holds the promise of conformality when implanting large macroscopic features, the latter is far less obvious when trying to dope microscopic feature conformally. In fact the formation of conformal junctions in FINFET's with plasma based processes is quite challenging and relies on secondary processes such as resputtering, deposition and in diffusion etc. Their optimization is compromised by concurrent artifacts, sputter erosion being the most important one. In support of these developments the measurement and identification of conformality adequate metrology is required. For this purpose we have extensively used Scanning Spreading Resistance Microscopy (SSRM) as a means to characterize the vertical/lateral junction depths, the concentration levels and the degree of conformality. Characterization of the (3D)-underdiffusion can be achieved by a dedicated SSRM experiment and/or the Tomographic Atomprobe. As a complement to the SSRM technique we also developed a concept based on resistance measurements of fin's which allows to map the sidewall doping across the wafers and provides fast feedback on conformality.

A comprehensive model is developed from ab-initio calculations to understand the effects of co-implanted fluorine (F) on boron (B) and phosphorus (P) under sub-amorphizing and amorphizing conditions. The depth of the amorphous-crystalline interface and the implant depth of F are the key parameters to understand the interactions. Under sub-amorphizing conditions, B and P diffusion are enhanced, in contrast to amorphized regions where the model predicts retarded diffusion. This analysis predicts the F effect on B and P to be entirely due to interactions of F with point-defects.

Proper analysis of the Schottky barrier height extraction methods shows that sulfur implantation followed by anneal does not effectively reduce the Schottky barrier height of NiSi/n-Si contacts. Instead, the results for sulfur implanted samples are consistent with enhanced field emission due to an increased doping density of the surface region of the silicon. Sulfur has a large impact on contact resistivity for silicon with low initial doping concentration (<∼1017 cm−3), but little impact for silicon with high initial doping density (>∼1017 cm−3). Internal photoemission measurements show that the Schottky barrier height remains unchanged with sulfur implantation.

Articles you may be interested inInteractions of B dopant atoms and Si interstitials with SiO 2 films during annealing for ultra-shallow junction formation J. Appl. Phys. 97, 073520 (2005); 10.1063/1.1884246 Secondary ion mass spectrometry characterization of source/drain junctions for strained silicon channel metal-oxide-semiconductor field-effect transistors A nitride spacer with an underlying deposited tetraethoxysilane oxide, that behaves as a convenient etch stop layer, is a popular choice for sidewall spacer in modern complementary metal-oxidesemiconductor process flows. In this work we have investigated the effect of the silicon nitride spacer process on the boron profile in silicon and the related dose loss of B from the Si into the silicon dioxide. This is reflected as a dramatic decrease in the junction depth. We find that the silicon nitride influences the concentration of hydrogen in the silicon dioxide during the final source/drain anneal. The presence of H enhances the diffusivity of B in the silicon dioxide and thereby results in a significant dose loss from the Si into the silicon dioxide. In this work we have shown this dose loss can be lowered by altering the silicon nitride stoichiometry.

CMOS technology for 1.2V high performance applications is being scaled to sub-0.09pm physical nominal gate lengths and with effective gate dielectric thickness less than 2nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09pm (post gate reoxidation), and gate dielectric thickness of 2.7nm (nMOS), 3.0nm (PMOS) (inversion at 1.2V), nMOS and PMOS Idrive is 763 pA/pm and 333 pA/pm respectively, at 1.2V with maximum Ioff=5nA/pm. Gate-drain overlap in this work is -2 10 h i d e and bottomwall junction capacitance is reduced to 0.8 fF/pm2 (PMOS) and 1.1 fF/Fm2 (nMOS). With reduced parasitics and high drive current, the 1.2V technology FOM (Figure-of-Merit) is > 39GHz, meeting the roadmap trend.