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CMOS technology for 1.2V high performance applications is being scaled to sub-0.09pm physical nominal gate lengths and with effective gate dielectric thickness less than 2nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09pm (post gate reoxidation), and gate dielectric thickness of 2.7nm (nMOS), 3.0nm (PMOS) (inversion at 1.2V), nMOS and PMOS Idrive is 763 pA/pm and 333 pA/pm respectively, at 1.2V with maximum Ioff=5nA/pm. Gate-drain overlap in this work is -2 10 h i d e and bottomwall junction capacitance is reduced to 0.8 fF/pm2 (PMOS) and 1.1 fF/Fm2 (nMOS). With reduced parasitics and high drive current, the 1.2V technology FOM (Figure-of-Merit) is > 39GHz, meeting the roadmap trend.

M a n y high voltage p o w e r rectifier structures (P-i-N, S S D , M P S , S P E E D , SFD) h a v e been reported w i t h i m p r o v e d reverse recovery characteristics. This paper provides a comparative analysis of these rectifiers performed b y using identical drift region properties to obtain the forw a r d I-V, reverse I-V, and reverse recovery characteristics. Based upon this study, it is concluded that the trade-off b e t w e e n stored charge, leakage current, reverse recovery time and forward voltage drop is the best for the M P S and S S D rectifiers. These rectifiers also exhibit improved soft recovery during switching.

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