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A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed. Its features are the reduced hardware resources and the real-time variation of the values of the carrier and switching frequencies, of the phase and of the amplitude of the three-phase output voltages in addition to not require external reference signals or further processors, like Digital Signal Processor. The basic idea is to pre-calculate a set of normalized dwell-time for only one sixth of the α − β-plane and, then, to reconstruct through our architecture the effective dwell-times and the right inverter configurations by an optimized management of the memory. The architecture is implemented in a Field Programmable Gate Array Cyclone V using the 6% and the 1.01%, respectively, of the Look-Up Tables and of the Flip Flops and the experimental measurements show the goodness of the generated waveforms and the high numbers of degrees of freedom without the demand of Digital Signal Processor or Personal Computer.INDEX TERMS Digital controller, field programmable gate array, space vector pulse width modulation, three-phase DC/AC power converter.

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Driver posture and micro movements are main indicators of his attention and situation awareness, as well as of his capability to suddenly take control if necessary. Therefore, the real-time detection of wrong postures is essential to mitigate the risk of accidents. In this work we want to show that, by using a custom Convolutional Neural Network (CNN) for image processing, a very accurate driver posture recognition system can be realized by using a limited number of pressure sensors, grouped in a small carpet placed only on the seat of the driver, regardless of its shape. Data from the sensor carpet are converted in images reproducing the different pressure regions of the driver's body, so that the CNN can extract features and classify 8 postures with an average accuracy of 98.81 % in real-time. According to the edge computing paradigm, the CNN implements an end-to-end classification by exploiting a quantization scheme for weights and binarized activations to reduce the number of required resources and allow a compact and low-power HW implementation on a small FPGA. When implemented with a Xilinx Artix 7 FPGA, the CNN consumes less than 7 mW of dynamic power at an operation frequency of 47.64 MHz. Such frequency is compatible with a sensor Output Data Rate (ODR) of 16.50 kHz, fundamental in critical applications, requiring a continuous monitoring and real-time action. Results of a 130 nm CMOS standard cells synthesis have also been reported.