We present a "carrierless" design for the manufacturing of ultrathin Silicon wafers, which are used in e.g. TSV (Through Silicon Via) and power chip applications. A carrierless wafer is a wafer which has a thinned inner portion, usually thinner than 150 m, and a rim portion, which is stabilizing the wafer, so that the whole wafer can be handled without any additional support. In more detail, progress on 300 mm carrierless wafers and its compatibility with standard applications like RDL (Redistribution Layer) and bumping will be discussed

The performance and efficiency of solar cells depends strongly on influence of materials. Key topics for solar cell optimisation are presently silicon material properties and materials for cell metallisation. Optimisation of silicon is focussed e.g. on material properties such as impurity content, density of dislocation and grain boundaries in multi‐crystalline silicon which influence parameters like carrier lifetime, and therefore the cell efficiency. Improved characterisation methods of solar cells like electroluminescence and photoluminescence are combined with techniques such as thermography and LBIC to improve production process and materials. As a result cell efficiency will be increased. Optimisation of cell metallisation and module interconnects is strongly related to progress in paste materials for front side metallisation. Improved materials enable the use of higher emitter resistance and the printing of smaller metal lines, while reducing the series resistance of the solar cell. Progress in paste materials leads to increased solar cell efficiency for the standard cell process. The introduction of new metal pastes has to be combined with careful optimisation of the process window in soldering during module built‐up. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

3D and Through-Silicon Vias (TSV) simplify and speed-up the chip-to-chip communication. The usage will enable manufacturers to increase the device performance, while cost effectively reducing overall size. The key issue for this new technology is a cost-effective drilling of holes into the substrate and the possibility to realize high density multilayer redistribution and bump layers (RDL). The most promising approach is to use photolithography with various thin and thick resist applications to etch the vias by deep reactive ion etching (DRIE) and to build up the RDL applicable on substrates with high topography. The structures to produce TSVs do not seem to be a challenge in nowadays production. The diameters are typically 1 to 50 m resp. 20 to 200 m for bumps, while the front-end industry manufactures in 32 node today. But to establish 3D IC and TSV, the production preferably should be capable to provide cost-effective lithography on thinned wafers at competitive pric e levels. This paper will present a method to expand the current production limits of Mask Aligners. Using special features on the mask in combination with a novel illumination optics, it is possible to increase the throughput, the expose gap and/or decrease the minimum structure size. This kind of technologie will enhance the range of D wafer level packing lithography applications on high topography substrates. The so called "MO Exposure Optics" from SUSS stabilizes the illumination of mask-aligners and allows to freely shape the angular spectrum of the radiation on the mask. So it is possible to transfer well know principles in projection lithography to mask-aligner lithography like Optical Proximity Correction (OPC) or Source Mask Optimization (SMO). It enables also the usage of binary optical elements to enhance the production of high density TSV and RDL / bump structures

The demand of smaller form factors, multifunctional microelectronics and thereby the need for improved electrical performance and reliability is the key driver for the development of 3D technologies with through silicon vias (TSV). Different through silicon via approaches are available and have pros and cons regarding process integration. But in any case a front to backside alignment is necessary regardless if a via first, via middle or via last approach has been chosen. This paper discusses available alignment technologies and strategies which are needed for front to backside alignment on 3D TSV integration examples. Alignment results with a 300mm mask aligner for a 2.5D interposer application and a via last approach are shown. The top side overlay accuracy between filled through silicon vias and the next photoresist layer showed a variation of 3 sigma = 1.7 mu m. The overlay accuracy for the wafer backside between TSV and the first backside photoresist layer was doubled to 3 sigma = 3.4 mu m. The difference was caused by the used alignment method. Furthermore the influence of wafer deformation (warpage / bow) on backside alignment accuracy is discussed for an interposer application