A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing “TDM” technique in the circuit switching part in order to increase path diversity, thus improving throughput while sharing communication resources among multiple connections. Combining these two techniques allows mitigating the poor resource usage inherent to circuit switching. In this way Quality of Service “QoS” is easily provided for the streaming traffic through the circuit-switched sub-router while the packet-switched sub-router handles best-effort traffic. The proposed hybrid router architectures were synthesized, placed and routed on an FPGA. Results show that a practicable Network-on-Chip “NoC” can be built using the proposed router architectures. 7 × 7 mesh NoCs were simulated in SystemC. Simulation results show that the probability of establishing paths through the NoC increases with the number of sub-channels and has its highest value when combining SDM with TDM, thereby significantly reducing contention in the NoC.

No abstract

With the increasing capacity of FPGAs following the Moore's law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores.Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteristics such as scalability, flexibility, high bandwidth, have been proposed as a valid approach to meet communication requirements in SoC. Most of the current NoCs uses mesh topology. With mesh topology, central channels are significantly solicited This often leads to the congestion ofthe center area ofthe mesh. The solutionfor such situation is to add routers in the mesh or to use torus topology which, with the symmetry introduced on the routers in the opposite edges, has a good behavior to face congestion, and this, with a small increase of resources. In this paper, we propose a scalable implementation of a NoCfor FPGA using torus topology. We proposed router architecture, a routing algorithm and a solution to the problem introduced by the long wires in torus topology.

This paper proposes a hybrid Network-on-Chip "NoC" which takes advantage of the best of packet switching and circuit-switching in order to handle efficiently both besteffort and streaming traffics generated by real-time applications. The proposed hybrid NoC consists of two sub-networks: a circuitswitched sub-network and a packet-switched sub-network. The circuit-switched sub-network combines Spatial Division Multiplexing "SDM" and Time Division Multiplexing "TDM" in order to increase path diversity in the NoC and to improve resources usage, in this way, quality of service is easily provided for streaming traffic while the packet-switched sub-network handles the best-effort traffic. A 7*7 2D mesh NoC is built and simulated. Simulation results show that this approach allows an increase of the probability of establishing paths through the NoC, reducing thereby contention in the NoC with a reasonable hardware cost as shown in synthesis results.

No abstract