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Abruptness at tunnelling junction is a vital issue with doped tunnel field-effect transistor (TFET) to achieve improved electrostatic characteristics. This task is more problematic for charge plasma TFET (CP-TFET) because of large tunnelling barrier at the channel/source interface. In this regard, an effective approach has already been employed through implantation of a horizontal metallic splint (HMS) inside the dielectric region near channel/source joint for improved electrical behaviour of CP-TFET. However, placement of a vertical metal splint (VMS) provides contact for HMS and gate electrode, which gives magnificent analogue/DC characteristics for newer structure. Combination of HMS and VMS (i.e. double metal splint (DMS)) increases electron density at channel/source junction for improved electron tunnelling rate compared with only HMS structure. In this regard, a complete comparative analysis of DMS CP TFET (DMS-CP-TFET) is performed between CP-TFET and HMS-CP-TFET. Furthermore, consequence of length and work-function variation of DMS and HMS on DC/RF parameters is investigated in device optimisation part of this work.

In this work, the performance estimation of polarity controlled electrostatically doped tunnel field-effect transistor (TFET) is reported. The proposed device exhibits heavily doped n-type Si-channel with two distinctive gates, namely control gate (CG) and polarity gate (PG). First, the CG and PG work functions of 4.72 eV are considered to convert the layer beneath CG and PG of intrinsic type. Next, the PG voltage of −1.2 V is used at source side to induce a p+ region, so that, it follows the similar trend as like a n +-i-p + gated structure of conventional TFET. Silvaco ATLAS simulation of the proposed device shows I ON /I OFF ratio of ∼7.8 × 10 10 and OFF current is less than 1 fA, with high-k dielectric of gate material at V DS = 0.5, V. Finally, a minimum point subthreshold slope of 12 mV/decade at 300 K is achieved, which indicates that the proposed TFET has the potential to achieve better than ITRS low-standby-power switch performance.