Engineered or 'virtual' substrates are of interest to extend the range of epitaxially-grown semiconductor heterostructures available for device applications. To this end, elastically strain-relaxed square features up to 30 μm in size and having an in-plane lattice constant as much as 0.49% larger than the lattice constant of GaAs were fabricated from MOCVD-grown GaAs/In 0.08 Ga 0.92 As/GaAs heterostructures by the in-place bonding method, using either AlAs or Al 0.7 Ga 0.3 As as the sacrificial layer. TEM images show that the solution-bonded interface is flat with a network of sessile edge dislocations that accommodates the different in-plane lattice constants of the feature and the GaAs substrate and a small rotation of the bonded features. Micro-Raman spectroscopy, which has a spatial resolution of ∼1 μm, was shown to be useful for characterizing lattice mismatch strain 0.0023, i.e. with an order of magnitude lower sensitivity than high-resolution XRD.

Wafer bonding using an intermediate layer such as SiO 2 is now a standard method for the fabrication of engineered substrates in the semiconductor industry, the prime example being silicon-on-insulator (SOI) substrates. However, direct semiconductor-to-semiconductor bonding by this method has been less successful, since the surfaces to be bonded are typically exposed to air. With the in-place bonding method, semiconductor-to-semiconductor bonding occurs during removal of a sacrificial layer in an HF solution, in principle allowing for a bonded interface that is free of oxygen and other airborn contaminants. We have investigated the interface properties of in-place bonded GaAs/GaAs structures with both transmission electron microscopy and current-voltage measurements. The interface was found to be free of an oxide interlayer and microstructure imperfections. The specific electrical resistance is (2.2 ± 0.5) × 10 −4 Ω cm 2 , an order of magnitude lower than values reported for wafer bonded interfaces.