No abstract

The reduction of the critical current density in rapid single-flux quantum (RSFQ) circuits enables new application fields, like quantum computing and photonic detector readout. The low current density fabrication process creates new design challenges, such as lower stability against thermal fluctuations, violation of the lumped elements condition for microstrip inductances and increased sensitivity to the technological spread. To overcome these issues, we suggest a passive phase shifter as a promising alternative technique for superconductive phase dropping in the RSFQ electronics. Here, we study experimentally their applicability in high-speed RSFQ digital circuits. Conclusions are drawn about the impact of the passive phase shifters on the complexity, the speed and the bit error rate of the investigated RSFQ circuits. We demonstrate the successful operation of different circuits with implemented passive phase shifters at low and high speeds.

No abstract

The manufacturing process of LTS RSFQ circuits is quite similar to that of the semiconductor chips, thus providing the possibility of an ultra high-density packaging similar to the modern semiconductor logic circuits. However, the miniaturization of the interconnects does not enhance their performance. The present work highlights the impact of the parasitic interactions between the superconductive interconnects on the correct logical functionality and the upper bias current margins of the LTS RSFQ circuits.

We study the dependence between the JTL inductance and its SFQ pulse propagation speed. An optimal value, being far away from the generally established design rules, is found. The dependence of this optimal value on the JTL parasitics is also considered. The bias margins behaviour around the new optimum is presented.