No abstract

Phase Change Memory (PCM) has emerged as an attr~ctive candidate for next-generation non-volatile memory devices, For these applications, reliability is determined by the abili~y to retain the state of data in the device and support a specified number of re-writes without failure. In PCM technologies, retention is limited by the meta-stable amorphous state of the cell. For cycling endurance (re-writes), failure occurs due to either void formation in the active material or contamination of the heating element of the cell. With optimized process integration and cell programming, large array devices based on a 90nm PCM technology are able to support data retention to 10 years at 85°C and greater than 10 6 write cycles.

The authors report an improvement in electrical characteristics with operational cycles of phase change memory cells having Ge2Sb2Te5 as the active material. An increase in amorphous-state resistance and threshold voltage and decrease in crystalline-state resistance with cycling are observed, which can be explained by gradual compositional change of the memory material driven by the energy input during programming operations. It is also found that melting of the active volume is critical for such improvement in the electrical characteristics. A physical model is proposed based on an expanding cell active volume with operating cycles to self-consistently explain the reported electrical data.

To support reliable large array products, Phase-Change Memory (PCM) technologies must be able to retain data over the product's lifetime with very low defect rates. PCM stores data in a chalcogenide material which can be placed in either a high resistance amorphous phase or a low resistance crystalline phase. Data retention is limited by resistance loss of the amorphous phase of the material, a process that is controlled by the kinetics of crystallization. This paper presents array-level data retention results on a statistical distribution of PCM cells that shows the failure rate with temperature to be welldescribed by the Arrhenius equation and distributed lognormally with time. For typical cells, the retention capability exceeds 100,000 hours at 85°C and is capable of meeting product requirements. In non-optimized devices, however, we observe cells that fail earlier than the lognormal distribution would predict. The failure distribution of these cells is Weibull with time but shows similar temperature acceleration to the intrinsic distribution, indicative of a defect in the amorphous chalcogenide. Characterization of these cells shows that their retention behavior is erratic. Furthermore, it is not significantly changed by write cycling. We then show that this defect distribution can be suppressed by process architecture or write algorithm optimization. Retention data collected on cells at both the 180nm and 90nm lithography nodes show that the intrinsic behavior is maintained with process scaling.