Reliability characterization of Phase Change Memory

Abstract

Phase Change Memory (PCM) has emerged as an attr~ctive candidate for next-generation non-volatile memory devices, For these applications, reliability is determined by the abili~y to retain the state of data in the device and support a specified number of re-writes without failure. In PCM technologies, retention is limited by the meta-stable amorphous state of the cell. For cycling endurance (re-writes), failure occurs due to either void formation in the active material or contamination of the heating element of the cell. With optimized process integration and cell programming, large array devices based on a 90nm PCM technology are able to support data retention to 10 years at 85°C and greater than 10 6 write cycles.

LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory

“…An early report showed that every lOx increase in pulse energy results in 1000x lower endurance [13], [11]. Recent measurements of failure rates on fabricated PCM chips showed similar results -lOx more failures were observed when a cell is 60% overheated [7]. While strong systematic process variations (PV) might be miti gated through circuit design, e.g., current provision [28] or customized write circuit [15], there are still non-negligible variations at the chip level.…”

Improving privacy and lifetime of PCM-based main memory

“…Data retention, endurance, program and read disturbs are some of the basic reliability aspects that have been investigated recently [12] [18]. In this paper we assume that there exist failing mechanisms or process variations causing some PRAM cells fail earlier than others [9]. Since PCM may have failures at some point, we need a scheme to detect and correct errors in PRAM.…”

“…To keep track of the wear-out status of PRAM, we use the number of write-accesses to PRAM as a metric. We assume that the raw bit error rate increases as PRAM ages [9]. Therefore, we gradually increase the strength of ECC protection by allocating more ECC bits when PRAM is gradually worn out.…”

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations

“…However, PCRAM is still challenging for its reliability enhancement [4,5]. Recently, some methods have been proposed to improve the reliability of PCRAM by studying the material characteristics and improving the fabrication process.…”