.66. Dk, 68.37.Lp Crystallization of hafnia and zirconia and their alloys with silica and lanthana was studied in bulk and thin film samples by thermal analysis, X-ray diffraction and electron microscopy. Crystallization temperatures of hafnia and zirconia increase by more than 300 °C with increase of surface/interface area of the amorphous phase. Crystallization temperatures of zirconia and hafnia alloys with silica and lanthana increase with dopant content and exceed 900 °C for 50 mol% SiO 2 and LaO 1.5 . Energies for tetragonal HfO 2 and ZrO 2 interfaces with amorphous silica were derived from their crystallization enthalpies from silicates as 0.25 ± 0.08 and 0.13 ± 0.07 J/m 2 , respectively. The crystallization pathways in bulk powders and films of zirconia and hafnia can be interpreted as resulting from thermodynamic stabilization by the surface energy term of tetragonal and amorphous phases over monoclinic.

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HfO 2 films deposited via tetrakis diethylamido hafnium ͑TDEAH͒ precursor using MOCVD ͑metal organic chemical vapor deposition͒ are presented. TDEAH is a promising precursor candidate for the deposition of high permittivity gate dielectrics. We report the impact of process and annealing conditions on the physical and electrical properties of the film. Deposition and annealing temperatures influence the microstructure, density, and impurity levels of TDEAH HfO 2 films. Spectroscopic ellipsometry shows that film microstructure manifests itself in the optical properties of the film, particularly in the presence of a band edge related feature at 5.8 eV. An impurity analysis using Auger electron spectroscopy, secondary ion mass spectroscopy, and Raman spectroscopy, indicates that carbon impurities from the precursor exist as clusters within the HfO 2 dielectric. The impact of deposition temperature and annealing temperature on the capacitance vs. voltage and current density vs. voltage characteristics of platinum gated capacitors is studied. Correlation of physical film properties with the capacitance and leakage behavior of the TDEAH HfO 2 films indicates that impurities, in the form of carbon clusters, and low HfO 2 film density are detrimental to the electrical performance of the gate dielectric.As the smallest feature size on a microprocessor approaches 50 nm, the primary dielectric layer in the field effect transistor, referred to as the gate dielectric or gate oxide, will thin to below 15 Å. Around this thickness, electrical leakage current through the dielectric becomes excessive and is expected to cause problems due to either high power dissipation or circuit reliability. 1 One solution to this problem is to replace SiO 2 dielectrics with higher permittivity dielectrics. A higher permittivity dielectric can be thicker and still achieve the same capacitance as a thinner SiO 2 dielectric. The starting point for identifying possible replacements for SiO 2 dielectrics is to evaluate their thermal stability in direct contact with silicon. Reactions between the high permittivity dielectric and the silicon substrate or electrode are undesirable. Extensive thermodynamic calculations have been performed by Hubbard and Schlom, 2 identifying numerous binary and ternary oxides that are candidate materials. Some of the binary oxides that are leading contenders for replacing SiO 2 include: ZrO 2 , HfO 2 , Y 2 O 3 , and Al 2 O 3 . In addition, there are numerous ternary ͑or mixed͒ oxides that have also been predicted, or experimentally determined, to be stable in contact with silicon.In general, the class IIIB and IVB oxides tend to be the most thermodynamically stable oxides for potential use in integrated circuit manufacturing. Doping the IIIB and IVB oxides with Al 2 O 3 or SiO 2 increases the crystallization temperature. Such amorphous dielectrics are desirable because grain boundaries enhance diffusion of dopants from the electrode to the substrate and possibly contribute to electrical leakage. On the other hand, doping...

r e b i b . The devices fabricated for this study used undoped channel Perlectly self aligned Vertical Multiple Independent Gate Field regions and doped polpilimn gates forming depletion mode transistors. Effect Transistor (MiGFET) CMOS devices have been Since the polpilimn and sourddrain regions have similar heights a single fabricated. The unique process used to fabricate these devices implant was optimized for the polpilicon gate, extension a d sourcadrain allow them to been integrated with FinFET devices. Device and regions. The devices still have very good short channel and current circuit simulations have been used to explain the device and capability due to the double gate architecture. A copper backend process explore new applications using this device. A Novel application was used to make ccntact to the two gates, source and drain. of the MIGFET as a signal mixer has been demonstrated. The Electrical Measurement and Devlce Simulation undoped channel, very thin body, perfectly matched gates allow3 (Figures 2ac) shows the electrical characteristics of the NMOS MIGFET. charge coupling of the two signals and provide a new family of When both gates are under the Same bias, the device shows double applications using the MIGFET mixer. Since the process allows gated depletion mode characteristics (Figure 2a). In this mode the device integration of regular CMOS Double gate devicas and MIGFET has all the advantages of a normal FinFET like structure it has extremely devices this technology has potential for various Digital and low leakage, DlBL and close to 6 5 m V . d~ SS. Independently biasing the Analog Mixed-Signal applications. gates of the device the threshold voltage, gain and sub-threshold swing INTRODUCTION are modulated (Figure 2 b.c). The devices show good drive and short MOSFET technologies using gates on more than one side of a channel characteristics for the case when the gates are tied together. A thin channel have shown better short channel characteristics Similar behavior is demonstrated for PMOS MIGFET devices Figure (3e and are proposed as a replacement to planar devices [I-2). c). The sub-threshold swing degradation (Figure 48) and gain (Gm) These fin type devices have a single gate wrap around multiple sensitivity (Figure 4b.c) to second gate bias demonstrate Utat this device silicon surfaces. These devices offer excellent characteristics for is extremely useful for certain applications while it will be difficult to use a given bias across the gate. Independent gate electrcdes on for other digital applications where the sub-threshold swing degradation either side of these channels however enable the channel to be substantially degrades performance. separately biased. CMP and planar Double devices have been Simulation of a 2 D cross section (Figure 5 a,b) f u an NMOS under demonstrated to offer independent dwMe gate operations [4].strong negative gate 1 potential shows a parasitic hole inversion forming The use of CMP to Pndpoint over thin fins could make all the which screens the influence of g...

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