We explore the electrical characteristics of TiS 3 nanowire field-effect transistor (FETs), over the wide temperature range from 3 to 350 K. These nanomaterials have a quasi-one-dimensional (1D) crystal structure and exhibit a gate-controlled metal−insulator transition (MIT) in their transfer curves. Their room-temperature mobility is ∼20−30 cm 2 /(V s), 2 orders of magnitude smaller than predicted previously, a result that we explain quantitatively in terms of the influence of polar-optical phonon scattering in these materials. In the insulating state (<∼220 K), the transfer curves exhibit unusual mesoscopic fluctuations and a current suppression near zero bias that is common to charge-density wave (CDW) systems. The fluctuations have a nonmonotonic temperature dependence and wash out at a temperature close to that of the bulk MIT, suggesting they may be a feature of quantum interference in the CDW state. Overall, our results demonstrate that quasi-1D TiS 3 nanostructures represent a viable candidate for FET realization and that their functionality is influenced by complex phenomena.

We study temperature dependent (200 – 400 K) dielectric current leakage in high-quality, epitaxial chromia films, synthesized on various conductive substrates (Pd, Pt and V2O3). We find that trap-assisted space-charge limited conduction is the dominant source of electrical leakage in the films, and that the density and distribution of charge traps within them is strongly dependent upon the choice of the underlying substrate. Pd-based chromia is found to exhibit leakage consistent with the presence of deep, discrete traps, a characteristic that is related to the known properties of twinning defects in the material. The Pt- and V2O3-based films, in contrast, show behavior typical of insulators with shallow, exponentially-distributed traps. The highest resistivity is obtained for chromia fabricated on V2O3 substrates, consistent with a lower total trap density in these films. Our studies suggest that chromia thin films formed on V2O3 substrates are a promising candidate for next-generation spintronics.

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We fabricated graphene field-effect transistors (GFETs) with hybrid organic/inorganic gate dielectrics, in which parylene C is used as the organic component. The HOMO−LUMO gap of parylene is large enough to provide effective gate insulation, yet significantly smaller than that of the inorganic component (SiO 2 ) of the dielectric. This allows this polymeric material to serve as an effective "floating node" that may be programmed by applying large voltage pulses to the GFET drain. We identify the role of two types of trapping in these devices: the first is mediated by short-lived interfacial states at the graphene−parylene interface, while the second, which is responsible for the nonvolatile memory function, involves hot-carrier injection into long-lived trap states deep in the parylene layer. Retention measurements demonstrate that charge injected into the parylene interior may be retained over long decay times (months), thereby confirming the potential of graphene-on-parylene for nonvolatile memory implementations.

We investigate the transient response of N,N-diethyl-N-(2-methoxyethyl)-N-methylammonium bis­(trifluoromethylsulfonyl)-imide-based ionic liquid (IL) planar capacitors, studying this response over time scales ranging from as little as a few nanoseconds to as much as several days. Our measurements point to the existence of three distinct mechanisms for charging/discharging of the IL. The fastest of these is associated with the development of a standard polarization charge in the bulk of the liquid dielectric, which dominates at times less than ∼10–6 s. The second process is attributed to electric double layer formation, which is initiated after ∼10–6 but which takes as long as ∼10–2 s to reach completion. Finally, we also identify the presence of a pseudocapacitance that arises from electrochemical reactions; this process is only activated at voltages above ∼2.5 V and is relatively slow. Indeed, we find evidence that full discharging of this pseudocapacitance can take as long as 105 s (i.e., days). Overall, our findings provide useful insights into the mechanisms for slow ion dynamics in ILs and highlight the constraints that these dynamics place on the potential operational speed of IL-based transistors.