In this work, the integration and its electrical properties of a carbon nanotube (CNT) interconnect for semiconductor applications are presented. A series array of 1000 vias made of vertically grown CNTs was achieved with uniform electrical resistance within the wafer. The integration of CNT interconnection was implemented with conventional semiconductor processes by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning on the wafer. Multi walled CNTs (MWCNTs) as the interconnection, titanium nitride as the bottom electrode, and aluminum with a titanium contact layer as the top electrode were used. We demonstrated well-defined CNT via interconnect with 700 nm via holes on a full-sized wafer. A via resistance of 350 kΩ and a CNT density of 2.7×1010/cm2 were achieved with a small resistance variation within the wafer, which also corresponded to 51.3 kΩ per MWCNT 10 nm in diameter. Possible approaches to further decrease of electrical resistance are suggested.

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Ferroelectric (Pb,Sr)TiO 3 (PST) thin films with a perovskite structure were prepared by the sol-gel technique. PST precursor solutions were prepared from lead (II) acetate, titanium tetraisopropoxide, and strontium acetate hemihydrate with solvents of acetic acid and 2-methoxyethanol. The PST film fabricated on an Ir/SiO 2 /Si substrate with a perovskite structure exhibited a ferroelectric hysteresis curve. The Pb/Sr ratio of the PST films could be controlled, however the Ti composition was larger than the stoichiometric value. It is important to obtain stoichiometric PST films for device applications, such as ferroelectric random access memories and piezoelectric filters.

Plasma polymerized methyl methaclylate (ppMMA) thin films were prepared with various process conditions such as inductively coupled plasma (ICP) power, substrate bias power, working pressure, substrate heating temperature, substrate position, and monomer flow rate. Thickness, surface morphology, dielectric constant, and leakage current of the ppMMA thin films were investigated for application to organic thin film transistor as gate dielectric. Deposition rate of over 8.6 nm/min, dielectric constant of 3.4, and leakage current density of 8:9 Â 10 À9 A/cm À2 at electric field of 1 MV/cm were achieved for the ppMMA thin film prepared at the optimized process condition: plasma power of RF 100 W; Ar flow rate of 20 sccm; working pressure of 5 mTorr; substrate temperature of 100 C; substrate position of 100 mm. The ppMMA thin film was then applied to pentacene based organic thin film transistor (OTFT) device fabrication. The OTFT device with 80 nm thick pentacene semiconductor layer showed field effect mobility of 0.144 cm 2 V À1 s À1 and threshold voltage of À1:72 V. #

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