Next-generation passive optical networks (PONs) with upstream rates of 50 Gbit/s and beyond will require a new class of burst-mode transimpedance amplifiers (BMTIAs) that are linear to enable (digital) equalization of channel impairments. Such linear BMTIAs also enable higher-order modulation formats like 4-level pulse amplitude modulation (PAM-4). In this paper, we demonstrate operation of a novel linear BMTIA integrated together with a commercial off-the-shelf 25G-class avalanche photodiode (APD), achieving 50 Gbit/s non-return-tozero (NRZ) operation with a sensitivity of -23.7 dBm optical modulation amplitude (OMA) and dynamic range exceeding 21.7 dB and 100 Gbit/s PAM-4 operation with a sensitivity of -15.8 dBm OMA and dynamic range exceeding 15.4 dB, both at a bit error ratio (BER) of 10 −2 . In addition, fast burst-mode gaincontrol and balancing circuits limit loud-soft sensitivity penalties in the case of AC-coupled circuits to less than 1.3 dB. The chip was designed in a 0.13 µm SiGe:C BiCMOS technology, has an area of 1.2×1.7 mm² and consumes between 260 mW and 310 mW. This receiver paves the way to a next-generation class of BMTIAs, supporting the ITU-T G.9804.3 Amd 1 standard.

Co-design of photonic and electronic chips has become a necessity to realize highperformance transceivers. This paper will illustrate a number of recent developments of high-speed transceiver circuits including broadband driver amplifiers and transimpedance amplifiers.

High-dynamic-range and fast-response burst-mode receivers have become a prerequisite for time-division multiplexed passive optical networks (TDM-PON). Recent progress in high-rate burst-mode receiving technologies optimized for linear operation enables upstream equalization or DSP for future PONs.

New circuit architectures and technologies for high-speed electronic and photonic integrated circuits are essential to realize optical interconnects with higher symbol rate. As a consequence of the increasing speeds, close integration and co-design of photonic and electronic chips have become a necessity to realize high-performance transceivers with novel packaging approaches. Extensive co-design also enables the design of new electro-optic architectures to create and process optical signals more efficiently. This paper and presentation will illustrate a number of recent developments of application-specific high-speed electrooptic transceiver circuits including e.g. broadband driver amplifiers, transimpedance amplifiers, analog equalizers and multiplexer circuits for signal generation and reception at 100 Gbaud and beyond. The basic concepts and architectures, technological aspects, design challenges and trade-offs will be discussed.