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This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO 2 layer effect, zero-stress temperature, single and array vias, through and blind vias, as well as diameter and pitch of vias. From the results of this study, the zero-stress temperature has been successfully determined from experimental data. The KOZs based on the more than 10% change in carrier mobility (or 5% saturated current changes) have been identified by finite element numerical calculations associated with related piezoresistive coefficients. Numerical results of saturated current changes have been validated by good comparisons with experimental data. Based on the detailed analyses using this validated model, the key parameters affecting the KOZs will be presented and discussed in detail.

In this study, we successfully improved junction breakdown using millisecond flash anneal (MFLA) on a dynamic random access memory (DRAM) product. By replacing a rapid thermal annealing (RTA) process with MFLA after contact implantation, improvements in NMOS and PMOS junctions were observed and no degradation was found. Device simulation data show that the PMOS junction electric field (E-field) was reduced with MFLA and that MFLA has an advantage in junction profile tailoring. The behavior of gate-induced drain leakage (GIDL) at different process stages with different annealing temperatures was studied. The preheat and peak temperatures of MFLA were found to be correlated with GIDL improvement. The optimum condition in this study was 1200 C flash anneal with a 750 C preheat temperature. Bright field and weak-beam dark-field transmission electron microscopy images showed perfect dislocation loops and fault dislocation loops remaining in the {113} plane with a size of around 17 Â 20 nm in the junction area. V C 2011 The Electrochemical Society.