Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias

Chang, Minchen; Lin, Jengping; Shih, Steven; Wu, Tieh-Chiang; Huang, Brady; Yang, Jing‐Tang; Lee, P.-I.

doi:10.1109/ted.2003.812498

Cited by 36 publications

(4 citation statements)

References 10 publications

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“…We focused on the behavior of tail bits, because the initial sensing fail bit is generated by tail bits. [22][23][24] In our device, the cycling disturbance with the set state shows more severe deterioration than that with the reset state. The portion of fail bits is 7.5% with c-ISPP, but no fail bit is detected with a-ISPP after 10 5 program accesses.…”

Section: Analysis Of Cycling Disturbance With Adaptive Isppmentioning

confidence: 99%

Reliability analysis and yield enhancement of resistive random access memory with adaptive incremental step pulse programming sizing

Kim

Baek

Seo

et al. 2014

Jpn. J. Appl. Phys.

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We investigated the reliability of resistive random access memory (ReRAM) under two different types of incremental step pulse programming (ISPP) along with the yield enhancement by the customized programming pulses based on the susceptibility of memory cells. Adaptive step-size control of ISPP enabled by an analog-to-digital converter (ADC) based sense amplifier significantly reduces the cycling disturbance by 54% because of the decreased number of effective write accesses. The programming yield of ReRAM was further improved with a proposed write scheme. The defective ReRAM cells are classified as soft fail cells and hard fail cells by the ADC-based sense amplifier, and soft fail cells are rescued by using a modified programming pulse. Measurements verified that the programming yield drop of 3% is completely recovered by the program pulse shaping.

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Section: Analysis Of Cycling Disturbance With Adaptive Isppmentioning

confidence: 99%

Reliability analysis and yield enhancement of resistive random access memory with adaptive incremental step pulse programming sizing

Kim

Baek

Seo

et al. 2014

Jpn. J. Appl. Phys.

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“…Gate workfunction engineering, such as an in-situ boron-doped polysilicon gate (p+ poly gate) or negative word-line voltage is mandatory to suppress I off which degrades DRAM retention characteristics. 7,8) In this paper, a recessed-channel FinFET (RC-FinFET) is proposed to improve the I off -GIDL relationship and the advantage of using RC-FinFET is proved by the improved retention characteristics.…”

Section: Introductionmentioning

confidence: 99%

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

Yoshida¹,

Kahng²,

Moon³

et al. 2008

jjap

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Electronic states for two possible high-pressure phases (with the ThSi 2 structure and with the AlB 2 structure) of CaSi 2 are determined by means of a local density approximation band-structure calculation. We confirm that these polymorphs can be regarded as doped sp 2 networks of Si. However, a simple picture in terms of π-orbitals is not adequate for explaining the conduction bands, because (i) an s-like band, which is anti-bonding in sp 2 connections but bonding between segments of the network, appears and (ii) there is π -d hybridization between Si and Ca.

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“…The bits belonging to normal and tail distributions are called as normal and tail bits, respectively in this paper. Many studies [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] have been concentrated on finding the mechanism of tail distributions. There have been also many simulation studies 1,6,7) to understand the reason for the existence of tail bits.…”

Section: Introductionmentioning

confidence: 99%

“…[6][7][8] It has been also reported that gate-induced drain leakage (GIDL) current due to band-toband tunneling (BTBT) or band-to-defect tunneling (BTDT) is a plausible leakage source for the tail distribution. [10][11][12][13] Basically many researchers have shown that the dominant leakage component in DRAM cells is the generation current via traps derived by using generalized form of the Shockley-Read-Hall (SRH) model, 19,20) and the wide variation in the retention time originates from the distribution in locations and/or energy levels of traps. [6][7][8][9][16][17][18] To follow the trend of T ret toward the future generation of DRAMs, we should optimize the design parameters, including the storage capacitance, C S , the substrate bias, V BB , the number of the repair capability, process conditions and so fourth.…”

Section: Introductionmentioning

confidence: 99%

Statistical p–n Junction Leakage Model via Trap Level Fluctuation for Refresh-Time-Oriented Dynamic Random Access Memory Design

Kamohara

Kubota

Moniwa

et al. 2008

jjap

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We have developed a new model for the leakage current of a single tail bit of dynamic random access memories (DRAMs). This model can explain the leakage current of each tail bit quantitatively. To derive model equations, we assume that some bits containing one specific trap center become tail bits among all bits in a DRAM chip. The variation of the leakage current of tail bits is attributed to the fluctuation of the trap level. Extracted value of the average trap level is 0.677 eV, which is the close value of the trap centers generated by Cu and Fe. By introducing the trap level fluctuation model, we have successfully reproduced the distribution of the retention time for tail bits. We also have obtained a good agreement between model and experimental results of tail distributions as functions of process splits and the temperature by using the present model. As an example applied by the present model, we estimated the required number of the repairable bits for 1 Gbyte DRAM.

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Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias

Cited by 36 publications

References 10 publications

Reliability analysis and yield enhancement of resistive random access memory with adaptive incremental step pulse programming sizing

Reliability analysis and yield enhancement of resistive random access memory with adaptive incremental step pulse programming sizing

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

Statistical p–n Junction Leakage Model via Trap Level Fluctuation for Refresh-Time-Oriented Dynamic Random Access Memory Design

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