The self-rectifying memristor with electronic bipolar resistive switching shows forming-free, highly rectifying properties and low operating power. Furthermore, configuring the memristors in a vertical array structure provides a higher memory...

In‐memory computing using memristor‐based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high‐energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module‐enable signal and input‐checker bits.

This work provides an off‐chip training method for a one‐selector‐one‐resistor (1S1R) crossbar array (CBA) device with wire resistance (rcc) and nonlinear conductance (g i,j) of 1S1R devices for hardware neural network (HNN) applications. An iterative method is introduced to calculate the node voltages of the 1S1R CBA, which arises from the variable voltage drop through the wires with rcc and g i,j. Several mathematical approximations are introduced for fast and efficient calculation. The proposed method trains the HNN to have an inference accuracy of 85.9%, whereas the inference accuracy of HNN without the rcc consideration drops to 38.5%. The inference running time with the proposed method is 1% of the HSPICE‐based simulation for the given HNN structure. As the rcc increases, the inference accuracy declines due to the decreased device voltage from the target values. The worst voltage model is adopted to identify the design factors that affected the accuracy. A CBA with a size almost three times larger can be used for the HNN if the rcc is appropriately addressed under the given device conditions.

One‐Selector‐One‐Resistor Crossbar Array As the one‐selector‐one‐resistor (1S1R) crossbar array becomes realistic, a precise simulation model is required for futuristic memory and neuromorphic applications. In this modeling, the high read current, high nonlinearity of the selector layer, and finite wire resistance of the 1S1R should be considered for reliable hardware neural network application which works with the complex input patterns and readout currents through array wires. More information can be found in article number http://doi.wiley.com/10.1002/aisy.202100256 by Cheol Seong Hwang and co‐workers.