No abstract

3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).

No abstract

No abstract

Today System-on-a-Chip (SoC) is like a black hole which draws all the important IP/Cores in a digital system. Current SoC design methodologies are no longer adequate to meet the challenges of SoC design productivity, design quality and diminishing time-to-market window. This paper describes an innovative SoC platform integration and verification design methodology to enhance design productivity based on IP reuse and IP-XACT standard. Platform Integrator including RPTKit (Reusable Platform Toolkit) is developed to improve the efficiency and reliability in platform integration, and Platform Verifier to improve verification setup time and work efficiency. Several cases of SoC platform designs substantiate the validity and capability of the Platform Integrator and Verifier, which reduced the total SoC integration and verification time by more than 30%.