The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and highenergy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 pm and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central core of the track strucitures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard lowenergy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 pm. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.

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In this paper we explore the sensitivity of commercial static random-access memory devices to 14 MeV neutrons. The effects on bulk technologies are investigated as a function of supply voltage and angle of incidence. Monte Carlo simulations of nuclear interactions with device architecture are used for comparison with experimental data. This simulation analysis allows us to determine the key parameters of the device sensitivity as a function of the technology integration.