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We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget lor gate activation, made possible by short dillusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of LM. IntroductionRecent advances in CMOS device isolation schemes make possible greatly increased device packing density. However, aggressive scaling of the PTOX-NTOX separation to submicron regime (0.4-0.6pn for 0.18pm CMOS) makes closely spaced P-and NMOS dual-poly devices with connected gates susceptible to cross-doping ellects, irrespective of the choice of the gate metal. Ai these dimensions, the device characteristics can be adversely affected by dopant lateral dillusion not only in the gate metal but also in the polysilicon layer itsell. In this work, we describe a novel processing scheme that ensures that dopant diffusion distances during gate drive-in and activation are much shorter than distanceshes needed lor dopant cross-diffusion, The gate structures are based on the concept of buried, ultra-low energy gate implants, utilizing the new generation of highcurrent, low energy ion implanters that have only recently become available 11).

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