0.18 um modular triple self-aligned embedded split-gate flash memory

Mih, R.; Harrington, James A.; Houlihan, K.; Lee, Hyun Koo; Chan, Kim-Fung; Johnson, James A.; Chen, Bomy; Yan, Ji; Schmidt, Andrei; Gruensfelder, C.; Kim, Kisang; Shum, D.; Lo, C. C. H.; Lee, D.; Levi, A.; Lam, C.

doi:10.1109/vlsit.2000.852793

Cited by 22 publications

(9 citation statements)

References 2 publications

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“…The method is demonstrated in this paper by flash cells fabricated mainly by the 0.18 lm triple self-aligned split-gate flash method [5,6]. The FG oxide is thermal grown with a thickness of 9 nm.…”

Section: Fabrication Methodsmentioning

confidence: 99%

“…Among different split-gate memory cells, the self-aligned split-gate flash cell has attracted much research interest for its fast erase, modular process and compatibility to CMOS process [5][6][7][8][9][10]. It uses floating gate (FG) tip enhanced poly-to-poly (FG to select gate) F-N tunnelling for erase, and source side hot electron injection for program [11,12].…”

Section: Introductionmentioning

confidence: 99%

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Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

Dong¹,

Kong²,

Do³

et al. 2010

Solid-State Electronics

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Section: Fabrication Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

Dong¹,

Kong²,

Do³

et al. 2010

Solid-State Electronics

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“…6 shows the cell-size vs. technology node and the process flow for the vertical split gate with quadruple self alignment process technology with true 2F pitch metallization [1] that improves from triple self alignment technology [7].…”

Section: Quadrupled Self Aligned Ssi Vertical Fg Flow Processmentioning

confidence: 99%

An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory

Tran

Sarin

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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An experimental 0.11um 4.5F 2 1.8V multilevel 1Mb vertical floating gate split gate source side injection (SSI) test vehicle for Giga-bit NOR flash memory is shown for the first time. Novel coupled sense line programming for 25mV precise charge placement and novel low cell current ~10ua mode source follower sense amplifier is shown to enable high speed high density G-bit MLC NOR flash memory system.

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“…Therefore, its application to portable systems is highly promising due to the low power consumption during cell operation. In this paper, a triple self-aligned method [7] is demonstrated using a 0.13-m standard logic process. As a result, the cell size can be shrunk to 0.214 m F .…”

Section: Introductionmentioning

confidence: 99%

“…2(a), the cell cross section scanning electron microscope (SEM) picture shows that the FG and WL channel lengths are around 0.17 and 0.11 m, respectively. The spacer profile is sharper than that of the 0.18-m generation [7]. In addition, the transmission electron microscope (TEM) picture [Fig.…”

Section: Introductionmentioning

confidence: 99%

Shrinkable Triple Self-Aligned Field-Enhanced Split-Gate Flash Memory

Chu

Lin

Hsieh

et al. 2004

IEEE Trans. Electron Devices

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This paper demonstrates a shrinkable triple self-aligned split-gate Flash cell fabricated using a standard 0.13-mcopper interconnect process. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All the processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 m. It is comparable in area with a stacked-gate cell and can be less than 13F 2 . The cell is erased by using poly-poly Fowler-Nordheim tunneling with a sharp floating-gate edge to increase the electric field, and is programmed by source-side injection. As a result, this cell is highly suitable for low power applications and embedded products. Characterization shows considerable program and erase speed, up to 300 K times cycling endurance, and excellent disturb margins.

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0.18 um modular triple self-aligned embedded split-gate flash memory

Cited by 22 publications

References 2 publications

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory

Shrinkable Triple Self-Aligned Field-Enhanced Split-Gate Flash Memory

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