This integrated circuit stores 256 analog voltage levels in high density, non-volatile memory with -7.5mV resolution per level. By contrast, the multilevel storage capacity of a typical digital non-volatile memory is 4-levels per cell [ll. The integrated circuit operates over a voltage range of 2.5V to 5.5V. Previous analog storage implementation use a 5.0V supply for -12mV equivalent resolution per level in a 128k EEPROM C21.

An experimental 0.11um 4.5F 2 1.8V multilevel 1Mb vertical floating gate split gate source side injection (SSI) test vehicle for Giga-bit NOR flash memory is shown for the first time. Novel coupled sense line programming for 25mV precise charge placement and novel low cell current ~10ua mode source follower sense amplifier is shown to enable high speed high density G-bit MLC NOR flash memory system.