Trapped electrons and holes, and their dynamics, were visualized from spatially resolved capacitance–voltage (C–V) curves and dC/dV images using scanning capacitance microscopy. A trapped charge of 10−16–10−18 C, localized within 2 μm diam circular test structures, was imaged. The detrapping process of the trapped electrons can be explained with a quantum-mechanical tunneling model.

Scanning capacitance microscopy (SCM) and Kelvin probe force microscopy (KPFM) are used to image the electrical structure of a silicon pn junction under applied bias. With SCM, the carrier density inside a diode is imaged directly. With KPFM, the surface potential distribution of an operating diode is measured, revealing different behavior from that in bulk. The surface potential drop is extended deep into the lightly p-doped region at reverse bias, reflecting the existence of the surface space-charge region as confirmed by the numerical simulation.