As CMOS devices are scaled to deep submicron dimensions, BEOL manufacturability will be constrained by both global and short local interconnects. The constraints on BEOL manufacturability imposed by linewidth variabiIi9, random defects, signal integrity, and electromigration are considered for 250 and 180 nm technology. Our 250 nm projections are based on available information about Intel's 250 nm Katmai microprocessor. This design has been extended to 180 nm by doubling logic and memoly. We find that signal integrity is the greatest constraint and this could be alleviated by going to copper technology ' Introduction 1 9 2 2 2 0 2.0 2 0 As CMOS devices are scaled to deep submicron dimensions, interconnects will constrain BEOL manufacturing. It is useful to group these interconnects into three categories (long, medium, and short), since each category has a different effect on manufacturability and performance. Since clock cycle delays are greatly affected by long wire delays, long, global interconnects have the greatest effect on performance. Short, local interconnects will be expected to have the greatest effect on yield since they are the narrowest, most closely spaced metal lines. Between the shortest and longest interconnects are wires of medium pitch and length which are necessary tc. meet wireability requirements. Chip wiring strategies often use three corresponding wiring domains of different pitch, with the longest wires on the top metal level, the shortest wires on M1, and wires with medium pitch and length on intermediate levels.In the following sections we will examine the wiring strategies used in recent Intel processors, specifically the 250 nm Pentium I1 processor (Deschutes) and apply these results to the 250 nm Pentium I11 processor (Katmai). Since Intel generally does not change designs when moving to a new technology, the Katmai design is a reasonable approach to estimating the effects of a move to the 180 nm technology recently described by Intel. With these results as a guide, we consider the constraints interconnects are likely to impose on BEOL manufacturing for emerging submicron technologies. Wiring Strategies for Intel Processors0-7803-5217-3/99/$10.00 0 lB999 IEEE 304 Table 1 illustrates wiring strategies used by Intel for 250 and 180 nm technologies and their relationship to recent Intel processor designs. All interconnect technologies are AVSiO' with W vias. Since new technologies are generally introduced as shrinks for existing designs, the 350 nm Pentium I1 processor (Klamath) [2] was shrunk to the 250 nm technology (Deschutes) [3]. Similarly, the new Pentium 111 design was introduced in 250 nm technology (Katmai) [4]. One may anticipate a 180 nm shrink of this design using Intel's recently defined 180 nm technology [5]. Our RIPE [6] estimates indicate that Deschutes can meet wiring efficiency requirements without repeaters. However, the total wiring efficiency of 0.19 is below Yang's suggested value.of 0.25 [7], which we obtained for Klamath. This is reasonable since the areas of the...

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