Interconnect-dominated VLSI design

Ghosh, Prolay; Mangaser, R.; Mark, C.; Rose, Kenneth

doi:10.1109/arvlsi.1999.756042

Cited by 8 publications

(2 citation statements)

References 12 publications

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“…With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power dissipation. The number of long interconnects doubles every 3 years [4], further increasing the importance of onchip interconnect.…”

Section: Ntrs 1997 Predictionsmentioning

confidence: 99%

Introduction to Interconnects

Saini

2015

Low Power Interconnect Design

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Section: Ntrs 1997 Predictionsmentioning

confidence: 99%

Introduction to Interconnects

Saini

2015

Low Power Interconnect Design

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“…Too slow and too few interconnects between VLSI circuits cause a bottleneck in the communication between processor and memory or, especially in multiprocessor systems, among the processors itself [1][2][3][4] . These problems on the interconnection side are due to fundamental physical reasons of electronic links and can not be solved by technological progress.…”

Section: Introductionmentioning

confidence: 99%

Parallel optical interconnects with mixed-signal OEIC and fibre arrays for high-speed communication

Fey¹,

Hoppe²,

Loos³

et al. 2004

SPIE Proceedings

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We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8×8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.

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Optimum wire sizing of RLC interconnect with repeaters

El-Moursy

Friedman

2004

Integration

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Interconnect-dominated VLSI design

Cited by 8 publications

References 12 publications

Introduction to Interconnects

Introduction to Interconnects

Parallel optical interconnects with mixed-signal OEIC and fibre arrays for high-speed communication

Optimum wire sizing of RLC interconnect with repeaters

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