Optimum wire sizing of RLC interconnect with repeaters

El-Moursy, Magdy A.; Friedman, Eby G.

doi:10.1016/j.vlsi.2004.04.001

Cited by 50 publications

(6 citation statements)

References 49 publications

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“…To decrease the interconnect delay in modern IC design, a long interconnect is divided evenly into smaller segments with repeaters inserted between each segment (each repeater is responsible for driving one segment). Thus, the timing transmission is significantly reduced [16]. A traditional two-repeater chain structure using SGAA that is employed regularly in driving a long chain of interconnects is depicted in Fig.…”

Section: Interconnect Boosting Techniquementioning

confidence: 99%

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

Lee

Ryu

Kim

2015

IEICE Electron. Express

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Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore's law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAAbased designs. Keywords: gate-all-around (GAA), multi-gate transistor, interconnect, repeater, boosting technique, RC delay Classification: Integrated circuits References

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Section: Interconnect Boosting Techniquementioning

confidence: 99%

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

Lee

Ryu

Kim

2015

IEICE Electron. Express

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“…Compared with the other two parts, the short-circuit power is so small that it can be ne-glected in the power model. For a long interconnect with length of L w , considering power dissipated by the CLC, the total power dissipation can be written as the following equation (7). And h L expresses the size of the left-most inverter in Fig.…”

Section: Power Dissipation Modelmentioning

confidence: 99%

“…In order to meet performance requirements arising from increasing clock frequency and increasing complexity, many methods, such as optimal repeater insertion (ORI), [1,2] wire spacing and sizing, [3] lowswing circuit, [4,5] bus encoding, [6] and diverse combinations of them, [7,8] have been proposed. Uniform repeater insertion is an effective technique for driving long interconnects and the authors in Ref.…”

Section: Introductionmentioning

confidence: 99%

A novel low-swing interconnect optimization model with delay and bandwidth constraints

朱樟明¹,

郝报田²,

杨银堂³

et al. 2010

Chinese Phys. B

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Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

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“…These RLC transmission line when running parallel to each other have capacitive and inductive coupling, which makes the design of interconnects even more important in terms of crosstalk. Much of the research efforts till date have been directed towards reducing delay and power dissipation only (Bakoglu and Meindl, 1985; Bakoglu, 1990; Ismail et al , 2001; El‐Moursy and Friedman, 2003, 2004; Kahng and Muddu, 1997; Adler and Friedman, 1998; Banerjee and Mehrotra, 2001; Ismail and Friedman, 2000). Crosstalk noise effects have not been given much concern.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects

Kaushik

Sarkar²,

Agarwal³

et al. 2006

Microelectronics International

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If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay. Design/methodology/approach -Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 mm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W n ¼ 3.9 mm and W p ¼ 7.8 mm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V A switching from low to high; input to line B, i.e. V B switching from low to high; input to line A i.e V A switching from low to high; input to line B, i.e. V B switching from high to low; V A switching from high to low and V B at static low; V A switching from high to low and V B at static high. Findings -This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power-delay-crosstalk-product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP. Originality/value -The PDCP criterion is introduced as an efficient technique to insert ...

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Optimum wire sizing of RLC interconnect with repeaters

Cited by 50 publications

References 49 publications

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects

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