This study examined the electrophysiological correlates of auditory and visual working memory in children with Specific Language Impairments (SLI). Children with SLI and age-matched controls (11;9 – 14;10) completed visual and auditory working memory tasks while event-related potentials (ERPs) were recorded. In the auditory condition, children with SLI performed similarly to controls when the memory load was kept low (1-back memory load). As expected, when demands for auditory working memory were higher, children with SLI showed decreases in accuracy and attenuated P3b responses. However, children with SLI also evinced difficulties in the visual working memory tasks. In both the low (1-back) and high (2-back) memory load conditions, P3b amplitude was significantly lower for the SLI as compared to CA groups. These data suggest a domain-general working memory deficit in SLI that is manifested across auditory and visual modalities.

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T his paper is broken down into four major sections. Each section will describe one of the major concepts or conclusions of this paper. The first will discuss the electrical engineering concept of hardware timing analysis. We will talk about how we perform static system timing on hardware. This concept is applicable to any number of complex hardware designs, from a PC to a high-end mainframe. The second section will discuss the project management concept of critical path analysis. We will provide an overview of these concepts in a format and style that lends itself to easily recognizing the correlation between critical path analysis and hardware system timing. The third section will discuss the correlation between the two concepts discussed in the first two sections. We feel that it will become obvious from this discussion that these two concepts are actually one and the same. Even though these processes and algorithms have never, to the best of our knowledge, been studied or derived in common, they are actually one set of algorithms and one mathematical concept. Finally, in the fourth section, we will consider what we can learn from the observation that hardware system timing analysis and critical path analysis are one and the same.

Buried engincoring changc ( H I i C ) is a method oflaying out engineering change ( I X ) wircs within a multi chip module (MCM) at original build time for later me.These BEC lines are used for repairs, ECs and temporary rues ( T X ) . Since repaw and TX connections are handled essentially as ECs, they will not be di~tittguished after this point.REC.' has posed several new chllcnges including how to elcctrically model, time and verify these complex multifacctcd structures, in the simplest way. BEC provides for 100% EC coverage on most MC'Ms. This paper discrcsses the modeling used to accurately predict delay, validate electrical integrity, nnd add a degree of flexibility to the wiring process. HistorylPurposePrevious I B M machine's M C M s were ECcd arid repaired exclusively with discrete jumper wires. Some of these discrele jumper wires were very long and OCCAsionally caused reliability problems, as well >IS electrorriagrrclic itrtcrf'ercncc ( K M I) prohlcins.'I'he UEC hardware methodology was dcvclopcd for improved rtAiability and rcduccd I

This paper discusses a methodology which allows a .package designer to totally optimize his package based on timing and wiring requirements, within one integrated tool. If all nets are optimized for timing, both critical and non-critical, then the package is not optimized from a wirability point of view. If all nets are optimized for wirability, then the package is not optimized from a timing perspective. If timing critical nets are optimized for timing and non-timing critical nets are optimized for wirability, then we have an optimized system. This paper discusses how the use of innovative net typing and pin ordering techniques allows for the maximum optimization of package hardware designs. The paper will further discuss a new approach to automatically apply the same net typing and pin ordering techniques to nets which violate all legal wiring rules and thus can not be mapped to a wiring rule solution through conventional means.