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This paper describes an on-chip intellectual property (IP) testing platform, Universal High Frequency Test structure (UHFTs), which makes logic, memory, and analog / mixed-signal IPs at-speed testable in the same testing structure. Any functional testing pattern can be loaded from an external pattern generator or a tester through standard 5-pin JTAG interfaces operating at 10MHz or below. The on-chip multichannel JTAG interface and elastic buffers convert an externally supplied pattern to an on-chip at-speed high-frequency pattern. The pattern can have address, data, and control fields. Each field is applied as input to a DUT in any one of 16 available DUT sites, fully synchronized to the on-chip global clock. The output from the DUT is captured at-speed and stored in an output buffer. The content of the output buffer is read out to an external tester through the elastic-buffer and JTAG interfaces under a program control. UHFTs, implemented in TSMC 28-nm High Performance CMOS process, has been successfully used in digital, including ATPG, BIST, and vector-based tests with the capability of mixed-signal and analog tests. UHFTs have been designed with a frequency goal of 4 GHz in TSMC 28-nm CMOS process in the slow corner.

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