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Wang Yi-Yu(王弋宇) a) , Shen Hua-Jun(申华军) a) † , Bai Yun(白 云) a) , Tang Yi-Dan(汤益丹) a) , Liu Ke-An(刘可安) b) , Li Cheng-Zhan(李诚瞻) b) , and Liu Xin-Yu(刘新宇) a) a)

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In this paper, with Sentaurus TCAD simulation, the trench/planar MOSFET (TPMOS) shows a much lower electric field in gate oxide and a smaller gate charge than the traditional trench MOSFET (TMOS) and commercial double trench MOSFET (DTMOS). Besides, compared with DTMOS, the TPMOS also has a smaller specific on-resistance. These advantages make the TPMOS more suitable for being integrated with a Schottky barrier diode (SBD) to reduce both conduction loss and switching loss. Therefore, the trench/planar 4 H-SiC MOSFET integrated with SBD (TPSBD) is firstly proposed and studied. For the TPSBD, the static simulation results show that the maximum reverse current without the body diode turning on is 1320 A cm −2 in the third quadrant. In the double pulse test with a load current of 1000 A cm −2 , the body diode of the TPSBD is successfully suppressed. However, the body diodes of the other three MOSFETs turn on and contribute 75% of the freewheeling currents, even though an external SBD is anti-parallel with these MOSFETs. The body diodes still contribute 25% of the freewheeling currents, even though the active area of the anti-parallel SBD increases three times. Compared with TMOS, DTMOS and TPMOS, the reverse recovery charge of the TPSBD reduces by 91%, 88% and 96%, respectively. The total switching loss of the TPSBD also reduces by 83%, 71% and 66% in contrast with TMOS, DTMOS and TPMOS, respectively. Therefore, the TPSBD is a superior choice for low reverse recovery charge and low switching loss application.