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To avoid high temperature annealing in improving the source/drain (S/D) resistance (R DS) of amorphous indium–gallium–zinc-oxide (α-IGZO) thin-film transistors (TFTs) for flexible electronics, a simple and efficient technique using a sputtering-deposited n+-ZnO buffer layer (BL) sandwiched between the S/D electrode and the α-IGZO channel is proposed and demonstrated. It shows that the R DS of α-IGZO TFTs with the proposed n+-ZnO BL is reduced to 8.1 × 103 Ω as compared with 6.1 × 104 Ω of the conventional one. The facilitation of carrier tunneling between the S/D electrode and the α-IGZO channel through the use of the n+-ZnO BL to lower the effective barrier height therein is responsible for the R DS reduction. Effects of the chamber pressure on the carrier concentration of the sputtering-deposited n+-ZnO BL and the thickness of the BL on the degree of improvement in the performance of α-IGZO TFTs are analyzed and discussed.

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A surface roughening scheme with Si3N4-coated GaN nanowire (NW) arrays is proposed to improve the light extraction efficiency of GaN-based vertical light-emitting diodes (VLEDs). The scheme allows a graded refractive index that varies from 2.5 (GaN) to 1.9–2.0 (Si3N4) to 1 (air). Experimental results show that the use of 0.8-µm-long GaN NW arrays coated with a 250-nm-thick Si3N4 film enhances the light output power by 28.7% at 350 mA compared with that of regular VLEDs with a KOH-roughened surface. This enhancement is attributed to the Si3N4/GaN NW arrays effectively releasing total internal reflection and minimizing Fresnel loss.