A metal-nitride-oxide-silicon (MNOS) one-time-programmable cell with fast programming, high reliability, and fully low-temperature polycrystalline-silicon (LTPS) panel compatible process has been proposed for system-on-panel applications. This cell adopting tunneling programming scheme has a very wide reading window with superior program efficiency. Furthermore, fast program efficiency and high disturb immunity are both obtained in the LTPS panel technology by a divided voltage operation. Through channel FN programming, superior data retention and low-power operation are therefore achieved. The new embedded MNOS cell has provided a promising one-time-programming memory solution on the LTPS panels' applications.Index Terms-Fully compatible, low-temperature polycrystalline silicon (LTPS), one-time programmable (OTP), thin-film transistor (TFT).

Asynchronous Cross-Couple Read Assist (AC 2 RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.Introduction SRAM cell array speed variation is getting worse as technology shrinks and it impacts SRAM macro speed severely. The AC 2 RA circuitry scheme was invented for the first time for single-ended sensing to minimize speed variation and fabricated in 28nm HKMG process node. AC 2 RA circuitry improves SRAM cell array speed variation by 63.3%. Minimum operating voltage (Vccmin) from silicon testing result shows 15.3% improvement for 32k-bits SRAM macro. AC 2 RA circuitry has two important sensing activation signals, and the speed variation can be mitigated by 19.3% by firing them asynchronously. The access time for 16 cells per bit line (BL) with AC 2 RA circuitry can reach 140ps under 6σ SARM local variations and 215ps for 64 cells/BL array. In sum, AC 2 RA circuitry provides better cycle time by mitigating the impact from bit-cell variation, and faster access time by its unique sensing scheme.Operation of AC 2 RA Circuitry Figure 1 shows the Local IO (LIO) with AC 2 RA scheme and Configurable Assist Timer (CAT) -the controller of Read Assist Signals (AE1_U and AE2_U). The AC 2 RA consists of 4 cross-coupled NMOS transistors (N0-N3) and 1 enable transistor, N4. SGE_U enables BL_U/BLB_U pre-charge and Read-Assist function exclusively. AE1 and AE2 accompanied by BL/BLB development will turn on one of the pull-down paths to "assist" read operation, and PDS[0:1] can adjust their starting time. I-V simulation waveforms of assisted read-0 and read-1 are shown in Fig. 2. There are two phases for Read-0 operation, WL to AE1, and AE1 to the end of read cycle. Phase-1) the stored bit will favor pulling down BL, with slope S1. Phase-2) after AE1 and AE2 asserts, the assist circuitry can strengthen the pulling down operation to have the sharper slope of S2. This faster discharge time over bit line will trigger BLSO earlier to pull down GBL by N10. From current point of view, I BL from SRAM bit-cell brings phase-1 BL-discharge and I N1 by AC 2 RA can greatly help BL discharge to "0." The disturbance, I N0 , cannot rival I N1 and will be cut off by developing BL. Furthermore, the faster discharged BL will trigger cross-coupled PMOS devices connected to them [6], which brings BLB back to "1" level -it prevents read failure as well as gains maximum assist current. To the contrary, Read-1 discharges BLB faster by S2 but suffer from small disturbance by I N1 due to AE1. However, I N1 is still no matching with I BLB and I N0 such that BLSO remains "0" and GBL is untouched. This assist scheme is able to greatly suppress the impact from bit-cell variation. Compared with conventional single-ended design, AC 2 RA lowers the variation by 63.3%. Measurement Result and OptimizationThe silicon result of Vccmin is shown in Fig. 3. The test corner is sl...

A new built‐in trimming scheme boosting the driving current through analog programming of the driving pTFT is proposed. The current variation on the panel can be controlled within 1%. This blanket boosting scheme is demonstrated on a 2.4‐inch AMOLED panel with non‐uniformity improved from 8.1% to 4.9%.