A New Embedded One-Time-Programmable MNOS Memory Fully Compatible to LTPS Fabrication for System-on-Panel (SOP) Applications

Lee, Te-Yu; Chiu, Chih-Chieh; Liu, Yu‐Chung; Liu, Chih‐Chung; King, Ya‐Chin; Lin, Chiao–Chi

doi:10.1109/led.2008.2000831

Cited by 19 publications

(9 citation statements)

References 14 publications

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“…It shows that contact failure [10] occurs at a voltage of 2.9 V and 2.3 mA for the given 0.18-μm process. This comprises the programming condition, and the rupture of the contact provides permanent data retention that is not susceptible to stability problems due to baking as in other OTP structures [11]. The contact rupture is abrupt at the program voltage due to the small contact area.…”

Section: Resultsmentioning

confidence: 99%

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

Shi

Zhang

et al. 2011

IEEE Electron Device Lett.

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This letter describes the formation of one-timeprogrammable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm 2 . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.

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Section: Resultsmentioning

confidence: 99%

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

Shi

Zhang

et al. 2011

IEEE Electron Device Lett.

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“…ow-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) have attracted much attention for the applications of peripheral circuits and system-on-panel [1], [2]. High performance LTPS-TFTs require low threshold voltage (V th ), low off-state leakage current (I off ) and low subthreshold swing (S.S).…”

Section: Introductionmentioning

confidence: 99%

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

Guo

Yan

et al. 2019

Symp Digest of Tech Papers

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We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

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“…In addition to the display technology area, TFTs had also been studied as the memory device for the very-large scale integration (VLSI) application [3]- [5]. The fabrication process of Si-based TFTs is high compatible with VLSI technology and widely studied to achieve high performance characteristics for the realization of system-on-panel (SOP) [6], [7] and 3-D integrated circuits (3-D-ICs) [8], [9]. Low-temperature poly-Si (LTPS) TFTs with high-κ gate dielectric become a good candidate for the purposes of SOP and 3-D-ICs [10]- [13].…”

Section: Introductionmentioning

confidence: 99%

Asymmetric Driving Current Modification of CMOS LTPS-TFTs With ${\rm HfO}_{2}$ Gate Dielectric

Cheng-Yu

2014

IEEE Trans. Electron Devices

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In this paper, the asymmetric driving current I drv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO 2 gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO 2 /poly-Si interface. P-channel LTPS-TFT has much higher I drv ∼ 0.789 mA than the n-channel LTPS-TFT ∼ 0.274 mA under the same overdrive gate voltage. This asymmetric I drv is due to the characteristics of field effect mobility µ FE that p-channel LTPS-TFT has much higher hole µ FE ∼80.16 cm 2 /Vs than the electron µ FE ∼ 38.26 cm 2 /V s of n-channel LTPS-TFT. The modification of HfO 2 /poly-Si interface by O 2 plasma can enhance the electron µ FE ∼ 34% and reduce the hole µ FE ∼ 22.4%, resulting in balanced I drv of CMOS LTPS-TFTs that n-channel device shows I drv ∼ 0.553 mA and p-channel device shows I drv ∼ 0.590 mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO 2 gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits. Index Terms-3-D integrated circuits (3-D-ICs), HfO 2 , interfacial layer (IL), low-temperature poly-Si thin-film transistors (LTPS-TFTs), system-on-panel (SOP).

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A New Embedded One-Time-Programmable MNOS Memory Fully Compatible to LTPS Fabrication for System-on-Panel (SOP) Applications

Cited by 19 publications

References 14 publications

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

Asymmetric Driving Current Modification of CMOS LTPS-TFTs With ${\rm HfO}_{2}$ Gate Dielectric

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