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Despite the huge potential, integral passives form less than 3% of the replaceable discrete components. A major obstacle in bridging this gap has been the absence of a wider choice of materials that would conform to stringent performance requirements. Epoxy-ceramic composite dielectrics have been investigated in recent time towards the fabrication of integral thin film capacitors due to their compatibility with processing conditions for printed wire boards (PWB). Though many investigations in recent past have focussed on the dielectric properties of epoxy-ceramic composites it is surprising that investigations on the interfacial effects did not receive the attention they deserve.These effects are even more pronounced in nanocomposites as the influence of the interface turns dominant with decreasing size of the dispersed ceramic phase. Functionalization of barium titanate (BTO) nanoparticles with an organic silane was shown to improve the dispel-sion of the particles in the epoxy matrix and hence the rheological properties. The dielectric properties of a nanocomposite with a surface modified ceramic dispersant are likely intluenced in two ways (a) change in the microstructure of the composite brought about by the improved dispersibility and (b) change in the interfacial or Maxwell-Wagner-Sillars (MWS) polarization in the heterogeneous phase. Fundamental understanding of such intluences is important in the design of polymerinorganic nanocomposites.These intluences were investigated in the case of epoxy as well as polyvinylidene fluoride (PVDF) matrices with a dispersion of barium titanate nanoparticles at different volume fractions. Dielectric properties such as relative permittivity and impedance were investigated with frequencies up to IO7 Hz. The organic inodification of the interface was found to significantly intluence the processibility and dielectric properties.

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A quad high-speed transceiver cell is designed and implemented in 0.l3pm CMOS technology. To achieve low jiner while maintaining low power consumption, dual on-chip regulators are used for each dualloop PLL. The prototype chip demonstrates that the links can operate from 400Mb/s to 4GbIs with a bit enor rate < The quad cell consumes 390mW at 2.5Gb/s (95mW/link) under typical operating conditions with a 400mV output swing driving double terminated links.